any tips on how to decode or what i can do? Can it be de-compiled or what are my options or type of software to do so? Again the data i am trying to modify is solely specific to the M27C4002 chip. any point in the right direction is greatly appreciated, i am totally in the dark on this one but am highly motivated to figure this out!

If you have the board the chip came from it would help to know what address range the chip occupied. That might be a clue as to the kind of code in there.

 

If you have the board the chip came from it would help to know what address range the chip occupied. That might be a clue as to the kind of code in there.

If you have the board the chip came from it would help to know what address range the chip occupied. That might be a clue as to the kind of code in there.

A0-A19 is a shared bus between PROM chips and the i960(a+1) A1-A20

 

A0-A19 is a shared bus between PROM chips and the i960(a+1) A1-A20

Are you saying it occupied the entire space covered by those address bits?

 

Are you saying it occupied the entire space covered by those address bits?

Yes,
M27C4002 A0 goes to A1 on the i960
all the way up to
M27C4002 A17 goes to A18 on the i960,
also on the
M27C4002 Q0 goes to D0 on i960,
M27C4002 Q1 goes to AD1 on i960
THRU
M27C4002 Q15 goes to AD15 on i960

 

Are you saying it occupied the entire space covered by those address bits?

what do you think?

 

Does A0 on the i960 go to chip select on one of the M27C4002s and inverted A0 from the i960 go to chip select on the other M27C4002 ?

Les.

 

what do you think?

It is possible. What line on the i960 Goes to Chip Select (CS*) and what line goes to Output Enable (OE*). Replace the * with an overbar on the datasheet for the M27C4002.

 

Does A0 on the i960 go to chip select on one of the M27C4002s and inverted A0 from the i960 go to chip select on the other M27C4002 ?

Les.

Hi there Les, there is one M27C4002 chip and 2 - M27C801 chips that are a changed in a pair and one M27C1001, as far as the enable on the 4002

Does A0 on the i960 go to chip select on one of the M27C4002s and inverted A0 from the i960 go to chip select on the other M27C4002 ?

Les.

well the 4002 enable goes to this chip but i’m having a hard time finding a data sheet for this one

 

Hello,

That looks like a 74HC139 to me.
It is an Dual 2-to-4 line decoder/demultiplexer.

Bertus

 

Agreed. The modern SOIC-16 are almost identical minus the ON mark

 

It is possible. What line on the i960 Goes to Chip Select (CS*) and what line goes to Output Enable (OE*). Replace the * with an overbar on the datasheet for the M27C4002.

output enable goes to this chip below,

 

 

Hello

The RTC62423 is a clock/ date chip.

Bertus

 

ok all the Chip enable go to the 74hc139 which also connect to i960, see attached diagram that i created that shows all the chips/pins and where the connect to, again the data i want to disassemble or modify is the data on the 4002 chip only. Thanks for your help you guys are great on here!

 

It is possible. What line on the i960 Goes to Chip Select (CS*) and what line goes to Output Enable (OE*). Replace the * with an overbar on the datasheet for the M27C4002.

What do you think? what can i do if i look at this code? will i see the addresses in the code or how can i find a commonality that can help me determine what this code means

 

If you think you understand how words in the PROM map to words in the architecture look for words that implement the RETURN from a subroutine instruction. The words following the RETURN instructions might be entry points for subroutines. If you have a list of potential entry points you may be able to locate call instructions with those locations as a destination. If you find a destination and a RETURN instruction reasonably close together, decode the instructions in between to see if they make sense.

I don't remember how the i960 handles literals. If it puts them between a RETURN and the next entry point this will complicate you task.

 

If you think you understand how words in the PROM map to words in the architecture look for words that implement the RETURN from a subroutine instruction. The words following the RETURN instructions might be entry points for subroutines. If you have a list of potential entry points you may be able to locate call instructions with those locations as a destination. If you find a destination and a RETURN instruction reasonably close together, decode the instructions in between to see if they make sense.

I don't remember how the i960 handles literals. If it puts them between a RETURN and the next entry point this will complicate you task.

could you give me some examples to help me understand? where could i find how they lay out the the i960 return or instructions etc

 

could you give me some examples to help me understand? where could i find how they lay out the the i960 return or instructions etc

What you need is the instruction set reference. Knowing the particular model of the i960 will give you a clue to the memory map.

 

What you need is the instruction set reference. Knowing the particular model of the i960 will give you a clue to the memory map.

 

That's getting closer, but what we need is usually a document by itself called: "Instruction Set Reference", so we can identify the hexadecimal value of a teturn from subroutine instruction.