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Hi i’ve been out of the game for a long time and jumping back in now but i have a project i am working on that i need help with. I have a M27C4002 eprom that i got a bin(or hex) file from is there any way for me to make sense of this data or covert any of the system data back to code? any help or input would be greatly appreciated
EPROM DATA in a I960 Microcontroller system
- Thread starter brettsrt
- Start date
There were no microcontrollers in 1960. A computer required air conditioning and cable run through a sub floor. It is a long shot, but if you can dump the contents you might be able to disassemble the code if you try various alternatives.
INTEL i960
Wow. Blast from the past. I was writing for the I960 back in the early 90s.
If you can find a i960 disassembler, you can read the raw .asm.
But you will not be able to make sense of it. The original code was likely written in C.
Without knowing how the data was used, it would likely take a lot of guessing.
You could have spelled the part number correctly in the first place. In electronics tends to be a precise discipline, the case of a letter can make a huge difference...
Thus, the difference between C and .asm programmers.
i did it was a capital i so i suppose that was misleading
The data in question on this single EPROM, i am after this data cause you can change this chip to change what program is run so to speak, i have other chips(programs) data to compare to not sure if that would help, would it be easier to looking at the whole system? or what way should i go about this
So you're overcompensating now and using lowercase 'i' when it should be capital??
lol yes i suppose i am guilty of that
This thread made me decide to take a stroll down i960 memory lane. I dug up a bunch of old work. Here is the memory controller code I wrote for a 22V10 PLD written in ABEL (anyone remember that?):
Code:
module mem
title 'SRAM & EPROM Controller for PDA I960 CPU PCB'
mem device 'p22v10';
@Dcset
declarations
"clock
pmclk pin 1;
"plcc pin 2;
"inputs
be3, be2, be1, be0 pin 2,3,4,5;
"plcc pin 3,4,5,6;
wrrd, blast, ads pin 6,7,8;
"plcc pin 7,9,10;
ramce, romce,logce pin 9,10,13;
"plcc pin 11,12,16;
reset pin 11;
"plcc pin 13;
"outputs
we3, we2, we1, we0 pin 23,22,21,20 istype 'com';
"plcc pin 27,26,25,24 istype 'com';
wr, ready, active pin 18,17,16 istype 'reg,invert';
"plcc pin 21,20,19 istype 'reg,invert';
t0,t1 pin 15,14 istype 'reg,invert';
"plcc pin 18,17 istype 'reg,invert';
rden pin 19 istype 'reg,invert';
"plcc pin 23 istype 'reg,invert';
"power
gnd pin 12;
"plcc pin 14;
vcc pin 24;
"plcc pin 28;
x = .x.;
z = .z.;
c = .c.;
be = [be3,be2,be1,be0];
we = [we3,we2,we1,we0];
s = [active, ready, t1, t0];
idle = [1,1,1,1]; "s15
tw4 = [0,1,1,1]; "s7
tw3 = [0,1,1,0]; "s6
tw2 = [0,1,0,1]; "s5
tw1 = [0,1,0,0]; "s4
td = [0,0,1,1]; "s3
trw = [0,0,0,1]; "s1
u0 = [0,0,0,0];
u2 = [0,0,1,0];
u8 = [1,0,0,0];
u9 = [1,0,0,1];
u10 = [1,0,1,0];
u11 = [1,0,1,1];
u12 = [1,1,0,0];
u13 = [1,1,0,1];
u14 = [1,1,1,0];
equations
s.clk = pmclk;
wr.clk = pmclk;
we = !(!wr.fb & !be);
ready.oe = !rden.fb;
s.ar = !reset;
wr.ar = !reset;
rden.ar = !reset;
state_diagram s
state idle: if (!ads) then idle with {wr:=1;
rden:=1;} else
if (!ramce & !wrrd) then tw1 with {wr:=1;
rden:=0;} else
if (!ramce & wrrd & !blast) then tw1 with {wr:=0;
rden:=0;} else
if (!ramce & wrrd & blast) then tw2 with {wr:=0;
rden:=0;} else
if (!romce) then tw2 with {wr:=1;
rden:=0;} else
if (!logce) then tw3 with {wr:=1;
rden:=0;} else
idle with {wr:=1;
rden:=1;}
state tw4: if (!ads) then idle with {wr:=1;
rden:=0;} else
tw3 with {wr:=1;
rden:=0;}
state tw3: if (!ads) then idle with {wr:=1;
rden:=0;} else
if ( wrrd & blast) then tw2 with {wr:=0;
rden:=0;} else
if ( wrrd & !blast) then tw1 with {wr:=0;
rden:=0;} else
tw2 with {wr:=1;
rden:=0;}
state tw2: if (!ads) then idle with {wr:=1;
rden:=0;} else
if ( wrrd) then tw1 with {wr:=0;
rden:=0;} else
if (!wrrd) then tw1 with {wr:=1;
rden:=0;} else
idle with {wr:=1;
rden:=0;}
state tw1: if (!ads) then idle with {wr:=1;
rden:=0;} else
if (!wrrd) then td with {wr:=1;
rden:=0;} else
if ( wrrd & !blast) then td with {wr:=0;
rden:=0} else
if ( wrrd & blast) then td with {wr:=1;
rden:=0} else
idle with {wr:=1;
rden:=0;}
state td: if (!ads) then idle with {wr:=1;
rden:=0;} else
if (!wrrd & blast & (!ramce # !romce))
then tw3 with {wr:=1;
rden:=0;} else
if (!wrrd & blast & !logce) then tw4 with {wr:=1;
rden:=0;} else
if (!wrrd & !blast & !ramce) then idle with {wr:=1;
rden:=0;} else
if (!wrrd & !blast & (!romce # !logce))
then trw with {wr:=1;
rden:=0;} else
if ( wrrd & blast) then tw3 with {wr:=1;
rden:=0;} else
if ( wrrd & !blast) then idle with {wr:=1;
rden:=0;} else
idle with {wr:=1;
rden:=0;}
state trw: goto idle with {wr:=1;
rden:=0;}
"unused states -- go back to idle
state u0: goto idle;
state u2: goto idle;
state u8: goto idle;
state u9: goto idle;
state u10: goto idle;
state u11: goto idle;
state u12: goto idle;
state u13: goto idle;
state u14: goto idle;
test_vectors([reset,pmclk,ads,ramce,romce,logce,blast,wrrd,be3,be2,be1,be0] ->
[active,ready,wr,we3,we2,we1,we0])
" b
" l w
" r c a r r l a r b b b b a r b b b b
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,0,x,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1];
[1,c,1,1,1,1,1,x,x,x,x,x]->[1,z,1,1,1,1,1];
"Non burst read from RAM:
" b
" l w
" r c a r r l a r b b b b a r w w w w
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,c,0,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->Tw2 (2)
[1,c,1,0,1,1,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (3)
[1,c,1,0,1,1,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (4)
[1,c,1,0,1,1,0,0,x,x,x,x]->[1,1,1,1,1,1,1]; "->Tr (5)
[1,c,x,1,1,1,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->idle
"Non burst write to RAM
" b
" l w
" r c a r r l a r b b b b a r w w w w
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,c,0,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->Tw2 (2)
[1,c,1,0,1,1,0,1,0,0,0,0]->[0,1,0,0,0,0,0]; "->Tw1 (3)
[1,c,1,0,1,1,0,1,0,0,0,0]->[0,0,0,0,0,0,0]; "->Td (4)
[1,c,1,0,1,1,0,1,0,0,0,0]->[1,1,1,1,1,1,1]; "->Tr (5)
[1,c,x,1,1,1,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->idle
"Burst read from RAM
" b
" l w
" r c a r r l a r b b b b a r w w w w
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,c,0,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->Tw2 (2)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (3)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (4)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (5)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (6)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (7)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (8)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (9)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (10)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (11)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (12)
[1,c,1,0,1,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (13)
[1,c,1,0,1,1,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (14)
[1,c,1,0,1,1,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (15)
[1,c,1,0,1,1,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (16)
[1,c,1,0,1,1,0,0,x,x,x,x]->[1,1,1,1,1,1,1]; "->Tr (17)
[1,c,x,1,1,1,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->idle
"Burst write to RAM
" b
" l w
" r c a r r l a r b b b b a r w w w w
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,c,0,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->Tw3 (2)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,0,0,0,0,0]; "->Tw2 (3)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,0,0,0,0,0]; "->Tw1 (4)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,0,1,1,1,1,1]; "->Td (5)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,1,1,1,1,1]; "->Tw3 (6)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,0,0,0,0,0]; "->Tw2 (7)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,0,0,0,0,0]; "->Tw1 (8)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,0,1,1,1,1,1]; "->Td (9)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,1,1,1,1,1]; "->Tw3 (10)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,0,0,0,0,0]; "->Tw2 (11)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,0,0,0,0,0]; "->Tw1 (12)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,0,1,1,1,1,1]; "->Td (13)
[1,c,1,0,1,1,1,1,0,0,0,0]->[0,1,1,1,1,1,1]; "->Tw3 (14)
[1,c,1,0,1,1,0,1,0,0,0,0]->[0,1,0,0,0,0,0]; "->Tw1 (15)
[1,c,1,0,1,1,0,1,0,0,0,0]->[0,0,0,0,0,0,0]; "->Td (16)
[1,c,1,0,1,1,0,1,0,0,0,0]->[1,1,1,1,1,1,1]; "->Tr (17)
[1,c,x,1,1,1,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->idle
"Non-burst read from ROM
" b
" l w
" r c a r r l a r b b b b a r w w w w
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,c,0,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->Tw3 (2)
[1,c,1,1,0,1,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (3)
[1,c,1,1,0,1,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (4)
[1,c,1,1,0,1,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (5)
[1,c,1,1,0,1,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Tw (6)
[1,c,1,1,1,1,1,0,x,x,x,x]->[1,1,1,1,1,1,1]; "->Tr (7)
[1,c,x,1,1,1,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->idle
"Burst read from ROM
" b
" l w
" r c a r r l a r b b b b a r w w w w
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,c,0,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->Tw3 (2)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (3)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (4)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (5)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (6)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (7)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (8)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (9)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (0)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (11)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (12)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (13)
[1,c,1,1,0,1,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (14)
[1,c,1,1,0,1,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (15)
[1,c,1,1,0,1,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (16)
[1,c,1,1,0,1,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (17)
[1,c,1,1,0,1,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Tw (18)
[1,c,1,1,1,1,1,0,x,x,x,x]->[1,1,1,1,1,1,1]; "->Tr (19)
[1,c,x,1,1,1,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->idle
"Non-burst read from LOG ROM
" b
" l w
" r c a r r l a r b b b b a r w w w w
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,c,0,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->Tw4 (2)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (3)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (4)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (5)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (6)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Tw (7)
[1,c,1,1,1,1,1,0,x,x,x,x]->[1,1,1,1,1,1,1]; "->Tr (8)
[1,c,x,1,1,1,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->idle
"Burst read from LOG ROM
" b
" l w
" r c a r r l a r b b b b a r w w w w
" s l d a o o s r e e e e c d w e e e e
" t k s m m g t d 3 2 1 0 t y r 3 2 1 0
[1,c,0,x,x,x,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->Tw4 (2)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (3)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (4)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (5)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (6)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw4 (7)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (8)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (9)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (10)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (11)
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw4
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td
[1,c,1,1,1,0,1,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw4 (12)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw3 (14)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw2 (15)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,1,1,1,1,1,1]; "->Tw1 (16)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Td (17)
[1,c,1,1,1,0,0,0,x,x,x,x]->[0,0,1,1,1,1,1]; "->Tw (18)
[1,c,1,1,1,1,1,0,x,x,x,x]->[1,1,1,1,1,1,1]; "->Tr (19)
[1,c,x,1,1,1,x,x,x,x,x,x]->[1,z,1,1,1,1,1]; "->idle
end
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What I am saying is that if there was an instruction word of 32-bits, it might be spread across 2 parts. It is unlikely that half a word would be in the first 16 bits and the other half in the next 16 bits.
Who could forget ABEL and the Data I/O programmer with the interchangeable heads.
i see what your saying, is it possible that it only uses 16bit instead of 32bit for the word? the other chips on this board are a pair of M27C801 chips that are a changed in a pair (2 chips) and one M27C1001, which are 8 bit
Yes. IIRC, the i960 had a bus width bit which one could use to access 16 bit wide hardware.
But it's been a long time. I could be mistaken.
That's a lot of different nonvolatile chips making continued speculation extremely difficult. It is possible that the i960 had a rudimentary loader in one of the chips whose sole purpose was to load the data from another chip into RAM. Have a go at trying to decode it but probably a complete waste of time. I've seen serial NV FLASH chips used for this purpose among ADI DSP chips like TigerShark & Blackfin
any tips on how to decode or what i can do? Can it be de-compiled or what are my options or type of software to do so? Again the data i am trying to modify is solely specific to the M27C4002 chip. any point in the right direction is greatly appreciated, i am totally in the dark on this one but am highly motivated to figure this out!
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