Hello everyone,
I designed an EMG circuit using the AD620 instrumentation amplifier IC.
I am facing a problem with the EMG signal in a tiny range of 0.1 mV to 10 mV. When I simulate the circuit by changing its input voltage, the output voltage becomes very high (Low to high). Then, I have to change the value of the gain resistor in AD620. How do I fix this?

 

hi Pooja,
Welcome to AAC
Please post a circuit diagram of your project.
E

 

And a link to the datasheet of the part you are using.

ak

 

At least, describe the rest of the circuit, including inputs, outputs, feedback and power supply connection.
My visualization skills are fairly good, my mind-reading ability is very poor.

 

Hello everyone,
I designed the EMG circuit on the breadboard using an ad620 amp and a power supply for inputs +5v and -5v. When I apply the input voltage (amplitude -20 mV, frequency 100 Hz using a function wave generator), I receive an amplified voltage (1.4) of AD620. But when I am not applying any input voltage, I still receive an 8.5-volt output voltage. How to solve the problem.

 

hi Pooja,
Welcome to AAC
Please post a circuit diagram of your project.
E

 

I have attached the datasheet of AD620. This is the AD620s circuit design in LT SPICE. I am facing a problem with AD620 because it gives an 8.5-volt output without providing any input on the breadboard circuit design.

​

​

 

Hi Poojam,
Are you sure you have the model the pin numbers created by LTSpice using the AD620 sub circuit correctly connected?

Post me your AD620 model file and your asc file and I will check it out.
E

 

it gives an 8.5-volt output without providing any input

If the inputs were floating, then the output will saturate at one of the rails.
Connect both inputs to ground for that test.

 

* AD620A SPICE Macro-model
* Description: Amplifier
* Generic Desc: 30/36V Bipolar, Inamp, prec G=1-10,000
* Developed by: ARG/ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 - Added V2,V3,V12,V13 and D3,D4,D15,D16 to clamp inputs to Q3,Q4 to prevent output phase reversal.
* Copyright 1990, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/s...nTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* This version of the AD620 model simulates the worst-case parameters of the 'A' grade.
* The worst-case parameters
* used correspond to those in the data sheet.
*
* END Notes
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | ref
* | | | | | | rg1
* | | | | | | | rg2
* | | | | | | | |
.SUBCKT AD620A 1 2 99 50 46 20 7 8
*
* INPUT STAGE
*
I1 7 50 5.002E-6
I2 8 50 5.002E-6
IOS 3 4 0.5E-9
VIOS 21 3 125E-6
CCM 3 4 2E-12
CD1 3 0 2E-12
CD2 4 0 2E-12
Q1 5 4 7 QN1
Q2 6 21 8 QN1
D1 7 4 DX
D2 8 21 DX
R1 1 3 400
R2 2 4 400
R3 99 5 100E3
R4 99 6 100E3
R5 7 9 24.7E3
R6 8 10 24.7E3
E1 9 46 (11,5) 375E6
E2 10 46 (11,6) 375E6
V1 99 11 0.5
RV1 99 11 1E3
CC1 5 9 4E-12
CC2 6 10 4E-12
*
* DIFFERENCE AMPLIFIER AND POLE AT 1MHZ
*
I3 18 50 5E-6
R7 99 12 11.937E3
R8 99 15 11.937E3
R9 14 18 1.592E3
R10 17 18 1.592E3
R11 9 13 10E3
R12 13 46 10E3
Q3 12 13 14 QN2
Q4 15 16 17 QN2
R13 19 16 10E3
R14 16 20 10E3
C1 12 15 6.667E-12
EOOS 19 10 POLY(1) (38,98) 1.5E-3 223.872
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
D3 13 51 DX
D4 16 52 DX
V2 99 51 0.7
V3 99 52 0.7
D15 53 13 DX
D16 54 16 DX
V12 53 50 0.7
V13 54 50 0.7
*
* GAIN STAGE AND DOMINANT POLE AT 0.667HZ
*
R16 25 98 35.810E9
C2 25 98 6.667E-12
G1 98 25 (12,15) 83.776E-6
V6 99 26 1.53
V7 27 50 1.33
D7 25 26 DX
D8 27 25 DX
*
* POLE AT 10MHZ
*
R17 40 98 1
C3 40 98 15.916E-9
G2 98 40 (25,98) 1
*
* COMMON MODE STAGE WITH ZERO AT 708HZ
*
E3 36 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
R18 36 38 1E6
R19 38 98 1
C5 36 38 224.812E-12
*
* OUTPUT STAGE
*
GSY 99 50 POLY(1) (99,50) 1.1725E-3 3.125E-6
RO1 99 45 250
RO2 45 50 250
L1 45 46 1E-6
GO1 45 99 (99,40) 4E-3
GO2 50 45 (40,50) 4E-3
GC1 43 50 (40,45) 4E-3
GC2 44 50 (45,40) 4E-3
F1 45 0 V4 1
F2 0 45 V5 1
V4 41 45 1.65
V5 45 42 1.65
D9 50 43 DY
D10 50 44 DY
D11 99 43 DX
D12 99 44 DX
D13 40 41 DX
D14 42 40 DX
*
* MODELS USED
*
.MODEL DX D(IS=1E-12)
.MODEL DY D(IS=1E-12 BV=50)
.MODEL QN1 NPN(BF=2.5E3 KF=0.7E-15 AF=1)
.MODEL QN2 NPN(BF=250 KF=0.5E-14 AF=1)
.ENDS AD620A

 

ok, Thank you.

 

Hi Pooja,
This is what I see using your circuit with my AD620 model.
E

 

hi Pooja,
This is a clip from my model, it is the same Issue as yours. OK.

* AD620 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 30/36V Bipolar, Inamp, prec G=1-10,000
* Developed by: ARG/ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 - Added V2,V3,V12,V13 and D3,D4,D15,D16 to clamp inputs to Q3,Q4 to prevent output phase reversal.
* Copyright 1990, 2012 by Analog Devices, Inc.

Pins:

Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | | ref
* | | | | | | rg1
* | | | | | | | rg2
* | | | | | | | |
.SUBCKT AD620 1 2 99 50 46 20 7 8

 

If the connections are as shown in post #7, there is NO WAY the operation can be even close to correct. Ever.
A product must be connected correctly to function as it should.

 

Hi Bill,
They are NOT pin numbers, they are Node assignment numbers, which are correct for LTSpice.

E
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply

* | | | negative supply
* | | | | output
* | | | | | ref
* | | | | | | rg1
* | | | | | | | rg2
* | | | | | | | |
.SUBCKT AD620A 1 2 99 50 46 20 7 8

 

OK on the numbers not being pin numbers. For those of us who do not use simulators it was not clear. One convention used in schematics that include IC devices is to have the pin number outside the block outline, and the function description, if it is provided, on the inside of the block outline. Some devices have the function described by the shape, like AND , OR, NAND, NOR, and inverters. That makes it clearer for those building a circuit as well as for those looking for how it functions.
"Wiring Diagrams" are only useful for folks building the devices.

 

Bill,
As it was a simulation based question, anyone that uses LTSpice knows that the Autogenerate function that it uses the Model sub.cir to produce a Basic model, it uses the conventional numbers for the Node assignments.
If a helper prefers the IC pin numbers and symbols, they can easily modify the basic model.

But in this Thread it is not necessary,

As you do not use or understand simulators, please stop belittling the work of other members who do.

E

 

Bill,
As it was a simulation based question, anyone that uses LTSpice knows that the Autogenerate function that it uses the Model sub.cir to produce a Basic model, it uses the conventional numbers for the Node assignments.
If a helper prefers the IC pin numbers and symbols, they can easily modify the basic model.

But in this Thread it is not necessary,

As you do not use or understand simulators, please stop belittling the work of other members who do.

E

I do not use simulators, that is correct. I do very well without them, in fact.
Now when somebody is seeking hep with something it is appropriate to speak to those asked in a language that is understood by all. That means, in this case, providing a circuit diagram with notations consistent with the components being used, instead of simulator nod numbers. Many of us understand the common functional notations normally used in integrated circuits. And when a component reference is posted nearby, we presume that it follows the same language. Thus my statement that the pin numbers shown were incorrect.
And not knowing what the TS was actually using, it was not likely that any would somehow modify that drawing.