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Hi everyone, I’m working on a final project in my Digital Electronic Circuits class, involving logical effort and EDP optimization in a digital circuit with a chain of NAND and INV gates. I’m trying to size each gate to minimize total EDP, and I need help understanding how to size inverters that aren't on the main path.
I calculated Cin for each NAND gate using the logical effort method by first finding G, B, H, and f_opt, and then using: \( Cin=\frac{g_i\cdot b_i\cdot Cout}{fopt} \), with branching effort being 1 for each.
Am I supposed to assume that each of the NAND gates' inputs see half of Cin? i.e., each NAND is symmetric?
Is it correct to say that B=1?
Also, in my diagram below, C0, C1, etc. are not capacitance. I didn't write down the Cin for each NAND gate, just the extra 20 fF load capacitances.
I calculated Cin for each NAND gate using the logical effort method by first finding G, B, H, and f_opt, and then using: \( Cin=\frac{g_i\cdot b_i\cdot Cout}{fopt} \), with branching effort being 1 for each.
Am I supposed to assume that each of the NAND gates' inputs see half of Cin? i.e., each NAND is symmetric?
Is it correct to say that B=1?
Also, in my diagram below, C0, C1, etc. are not capacitance. I didn't write down the Cin for each NAND gate, just the extra 20 fF load capacitances.
