I'm interested in the history of the logic design for the edge-triggered D flip-flop, as used in the SN7474. The design is composed of three set-reset latches (six NAND gates total) per flip-flop.

Does anyone know what year the SN7474 was introduced, or have an early datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st Edition?

The earliest datasheet I've found using this specific logic design for an edge-triggered D flip-flop is from a non-7400-series TTL chip, the Motorola MC3060/3160, which is a member of the MTTL III MC3000/MC3100 series.The MC3060 is covered in the Motorola 1968 IC databook, on page 4-138.

I've searched US patents for edge-triggered flip-flop design, but have not found one specifically for the three S-R latch design.

The subject came up as a result of a discussion on a private mailing list regarding the fact that the conventional J-K master-slave flip-flop design is NOT edge-triggered; pulses on J and/or K while the clock is high but stable can affect the Q (and not-Q) outputs of the FF at the following falling edge of the clock. That behavior is known as "pulse catching", and such a flip-flop is properly called pulse-triggered or level-triggered, but not edge-triggered. Early datasheets on J-K master-slave flip-flops actually had correct terminology and specifically stated that J and K should not change while the clock is high.

 

I have these catalogs:

Texas Instruments:
A Texas Instruments Application Report -- Oct. 1968
Logic design with Series 54/74 gates
A Texas Instruments Application Report -- Aug. 1969
TTL intgegrated circuits: Counters and registers
MSI/TTL Integrated Circuits from Texas Instruments -- about 1970
Bulletin CB-125
MOS/LSI Standard Products Catalog from Texas Instruments July 1971


I will look at them to see if any have information useful to you.

 

DEC was making flip-flops from discrete transistors in the form of Flip Chip modules prior to 1964. I would not be surprised if the concept of edge-triggered flip-flops was introduced before this time.

 

It is an interesting question and I'm not sure I have much to add...but....I would like to know what you come up.
The earliest mention of a flip-flop that I can find is here....

"At its March 1959 press conference, TI introduced two Kilby "solid circuits," a two-transistor flip-flop and a one-transistor phase-shift oscillator, each at $450." Check out the display

According to Wikipedia, the 74 series began with the 7400 first produced by TI in 1964. So, if you are eliminating the earlier non-74 TTL lines, it is no earlier thanr 1964. The TI data book from 1971 lists the 7474 and ls, and that it a few years before the data sheet you have. Not sure that is a legitimate link to post. So, somewhere between 64-71...so far. Hope it helps.

 

@Brouhaha
I looked at the old data I mentioned in post #2. No joy as to internal operation of TTL. In fact, these were mostly application notes for logic design. Not even very interesting from a historical view.

I looked at an old Motorola ECL data book. MECL II flip-flops such as the MC1013, MC1022 and MC1032 had the clock ac coupled to get edge sensitivity.

MOD EDIT: Corrected member alert tag.

 

The subject came up as a result of a discussion on a private mailing list regarding the fact that the conventional J-K master-slave flip-flop design is NOT edge-triggered; pulses on J and/or K while the clock is high but stable can affect the Q (and not-Q) outputs of the FF at the following falling edge of the clock. That behavior is known as "pulse catching", and such a flip-flop is properly called pulse-triggered or level-triggered, but not edge-triggered. Early datasheets on J-K master-slave flip-flops actually had correct terminology and specifically stated that J and K should not change while the clock is high.

So, I was looking around and was thinking that some information in "Designing with TTL Integrated Circuits", Texas Instruments, 1971, may be relevant.

P169 specifically mentions the caution that you mention with the J-K master-slave filp flop..


P 172 reiterates the caution while listing the devices


p 173 describes the 74110 with data lockout to prevent the issue, but, I am not seeing the relationship of the caution to the D type (also listed on p173) and of course the 7474 is listed as the D- type.


The data sheet from 1971 from TI, includes notes 3 and 4 (7-41) about set up and hold times for the 7474 and I don't see those in the later version.

I may simply not have the experience/knowledge but could you explain further?

 

Thanks for posting the info from Designing With TTL Integrated Circuits (which I have in my library), but the part of my post about J-K master-slave flip-flops was only to give the context for how my search came about, and I probably should have omitted it as it just confuses the issue.

I am really ONLY looking for information on the specific six-NAND-gate (configured as three S-R latch) logic design for the edge-triggered D flip-flop, as used in the SN7474 and MC3060. In another forum it was pointed out that the Motorola mW RTL MC778 appears to use a similar logic design. It appears that all three of these parts go back at least as far as 1967, but I haven't been able to find any evidence of parts using this logic design prior to 1967. The National Semiconductor DM8510 and Signetics 8828 also use this design, but I don't have evidence of them appearing as early as 1967.

The information I'm ideally hoping to find is where that logic design was used FIRST, and/or who invented it, but this may be hard to determine at a remove of at least 50 years from its origin.

 

Thanks for posting the info from Designing With TTL Integrated Circuits (which I have in my library), but the part of my post about J-K master-slave flip-flops was only to give the context for how my search came about, and I probably should have omitted it as it just confuses the issue.

I am really ONLY looking for information on the specific six-NAND-gate (configured as three S-R latch) logic design for the edge-triggered D flip-flop, as used in the SN7474 and MC3060. In another forum it was pointed out that the Motorola mW RTL MC778 appears to use a similar logic design. It appears that all three of these parts go back at least as far as 1967, but I haven't been able to find any evidence of parts using this logic design prior to 1967. The National Semiconductor DM8510 and Signetics 8828 also use this design, but I don't have evidence of them appearing as early as 1967.

The information I'm ideally hoping to find is where that logic design was used FIRST, and/or who invented it, but this may be hard to determine at a remove of at least 50 years from its origin.

Thanks much for responding. I did see your posts on another forum. I hope you will let us know what you end up finding.

 

Have you looked at RTL?

 

Have you looked at RTL?

Yes. Most of the early RTL flip-flops are not of the design I'm looking for, but the rather late Motorola mW RTL MC778 is. However, I have not been able to track the MC778, MC3060, or SN7474 definitively back to before 1967.

I've spent some time doing analysis of the circuit, as it is not immediately obvious how it works just looking at the logic diagram. I ended up writing my own crude event-driven logic simulator in Python to make it easier to automate portions of the analysis. One output of this is an automatically generated state diagram (using dot from the GraphViz program. However, there are 20 stable states to consider, so the automatically generated diagram is not very well-organized and not all that helpful. Still, I've attached a copy in case anyone is interested.

The key part of operation of the FF can be more easily understood by disregarding the asynchronous preset and clear inputs, which results in there being only eight states to consider. I've attached that state diagram as well.

 

I've spent some time doing analysis of the circuit, as it is not immediately obvious how it works just looking at the logic diagram.

Are you looking for the history of SN7474? Or are you just trying to figure out how it works?

 

I'm interested in the history of the logic design for the edge-triggered D flip-flop, as used in the SN7474. The design is composed of three set-reset latches (six NAND gates total) per flip-flop.

Does anyone know what year the SN7474 was introduced, or have an early datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st Edition?

The earliest datasheet I've found using this specific logic design for an edge-triggered D flip-flop is from a non-7400-series TTL chip, the Motorola MC3060/3160, which is a member of the MTTL III MC3000/MC3100 series.The MC3060 is covered in the Motorola 1968 IC databook, on page 4-138.

I've searched US patents for edge-triggered flip-flop design, but have not found one specifically for the three S-R latch design.

The subject came up as a result of a discussion on a private mailing list regarding the fact that the conventional J-K master-slave flip-flop design is NOT edge-triggered; pulses on J and/or K while the clock is high but stable can affect the Q (and not-Q) outputs of the FF at the following falling edge of the clock. That behavior is known as "pulse catching", and such a flip-flop is properly called pulse-triggered or level-triggered, but not edge-triggered. Early datasheets on J-K master-slave flip-flops actually had correct terminology and specifically stated that J and K should not change while the clock is high.

Flip flops were known in the times of vacuum tubes. Is that outside of your scope?

http://wikis.olin.edu/ca/doku.php?id=2014:vacuum_tube_sr_latch

 

Are you looking for the history of SN7474? Or are you just trying to figure out how it works?

I did the analysis and know how it works. I'm interested in the history of that particular logic design for an edge-triggered D flip-flop, whether SN7474 or other (e.g., MC3060, MC778, DM8520, S8828, etc.)

I doubt that the specific logic design significantly predates ICs, except maybe as a theoretical construct, because it would require too many tubes (or relays, etc.) to be practical compared to other FF designs. The low cost of transistors on an IC made it practical.

 

Flip flops were known in the times of vacuum tubes. Is that outside of your scope?

http://wikis.olin.edu/ca/doku.php?id=2014:vacuum_tube_sr_latch

Out of scope in so far as I stated that I was only looking for information on a specific design of a six-NAND-gate edge-triggered D flip-flop. Vacuum tube flip-flops tended to be S-R latches or T flip-flops.