DVI interfacing with TFP401x

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Joined Sep 18, 2016
I'm designing a project that will interface with DVI. I have chose the TFP401x to decode the video data but I have some confusion that I should get cleared up before I finish the schematic.
Firstly, the datasheet specifies it has a maximum pixel rate of 165 MHz, but how do I about calculating the pixel rate of individual resolutions (for example, the pixel rate of 1080p@60Hz or the pixel rate of 720p@144Hz)?
Secondly, the red, green and blue pixel outputs are all synced to ODCK, as well as the horizontal and vertical sync. Does that mean the pixel rate is equivalent to the clock speed of ODCK or is it slightly different due to the h/v syncing times?
Finally, once I know the clock speed of ODCK, I'm assuming in order to process the pixel outputs I need a processor that has a clock speed that either matches or is greater than the clock speed of ODCK?

Any help is appreciated!
Thanks, Bod

EDIT: I completely forgot I made a similar post about the same chip over a year ago o_O. Bit of an XY problem going on there, should have just asked these questions in the first place. I did end up picking the ATMega16L-8AU as the microprocessor, originally, but the whole board was expensive to have made and assembled so I left it to revisit it at a later date (now), but starting from scratch. I picked it as it has enough digital pins and the rate at which I needed to read the pixel data did not have to be that fast (and still doesnt), so the the lower clock speed wasn't a big concern. However, I realise now that perhaps if the clocks are different or the clock of the MCU is not a multiple of ODCK then at some point, as they fall out of sync, I would try and read during blanking time, which will probably just be equivalent to a black screen.
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