Hello,

I designed DVCC Instrumentation Amplifier with LTSPICE XVII. I used 0.18um Technology for FETs. The file is attached. When i simulate it i can take a good graph for DC characteristic but my frequency response seems wrong. Is there anyone who could help me. My Circuit and simulation results are attached.

 

Welcome to AAC!
Is there any reason you are using default MOSFETs and the 0.18u.txt file, rather than the supplied FET models from the library? I've never found the default MOSFET models to work well.

 

Welcome to AAC!
Is there any reason you are using default MOSFETs and the 0.18u.txt file, rather than the supplied FET models from the library? I've never found the default MOSFET models to work well.

Thank you!
This is actually a homework. The professor told us to simulate one of the dvcc applications from an article that he sent to us. And he said resize the trasistors w and l values using 0.18um technology. So i found the articles sizing values and i resize the w and l values. If i pick the transistor from the library as far as i know i have no chance to make this sizing. I am attaching the files for better understanding.

 

What you are doing requires a deep understanding of how the simulator interacts with different model specifications. There is not always a single universal model for a device type. It is possible that you have confused the LTspice simulation engine by the particular combination of parameters that you did specify in conjunction with those that you did not specify or accepted as a default.

Quoting from the LTspice Help file

M. MOSFET ​

There are two fundamentally different types of MOSFETS in LTspice, monolithic MOSFETs and a new vertical double diffused power MOSFET model.​

​

Monolithic MOSFET:​

​

Syntax: Mxxx Nd Ng Ns Nb <model> [m=<value>] [L=<len>]​

+ [W=<width>] [AD=<area>] [AS=<area>]​

+ [PD=<perim>] [PS=<perim>] [NRD=<value>]​

+ [NRS=<value>] [off] [IC=<Vds, Vgs, Vbs>]​

+ [temp=<T>]​

​

M1 Nd Ng Ns 0 MyMOSFET​

.model MyMOSFET NMOS(KP=.001)​

​

M1 Nd Ng Ns Nb MypMOSFET​

.model MypMOSFET PMOS(KP=.001)​

​

Vertical double diffused power MOSFET:​

​

Syntax: Mxxx Nd Ng Ns <model> [L=<len>] [W=<width>]​

+ [M=<area>] [m=<value>] [off]​

+ [IC=<Vds, Vgs, Vbs>] [temp=<T>]​

​

The MOSFET's model card specifies which type is intended. The model card keywords NMOS and PMOS specify a monolithic N- or P- channel MOSFET transistor. The model card keyword VDMOS specifies a vertical double diffused power MOSFET.​

​

As you can see the number of pins and the list of parameters is not the same. When there is a conflict in what it sees you trying to do it tries to make a decision about what you meant and proceeds. It does NOT throw any kind of exception or error. This decision can of course result in garbage for the output.

From a cursory examination of the symbol definition files "nmos.asy" and "nmos4.asy" it appears the for a monolithic device you should choose the "nmos4.asy" device since it has 4 pins.


I see from your text file that the model cards do not have any connection with the number of pins used in the symbol. In order to investigate further you should package up your files and post them.

I see another problem from the 0.18um.txt file and that is a Level 7 model is NOT defined for LTspice. It does have Levels 1-6 and 8 defined. Maybe you should consult with your professor on how to proceed.

From the LTspice Help file

M. MOSFET ​

There are seven monolithic MOSFET device models. The model parameter LEVEL specifies the model to be used. The default level is one.​

​

level model​

​

------------------------------------------------------​

​

1 Shichman-Hodges​

​

2 MOS2(see A. Vladimirescu and S. Liu, The Simulation of MOS Integrated Circuits Using SPICE2, ERL Memo No. M80/7, Electronics Research Laboratory University of California, Berkeley, October 1980)​

​

3 MOS3, a semi-empirical model(see reference for level 2)​

​

4 BSIM (see B. J. Sheu, D. L. Scharfetter, and P. K. Ko, SPICE2 Implementation of BSIM. ERL Memo No. ERL M85/42, Electronics Research Laboratory University of California, Berkeley, May 1985)​

​

5 BSIM2 (see Min-Chie Jeng, Design and Modeling of Deep-Submicrometer MOSFETs ERL Memo Nos. ERL M90/90, Electronics Research Laboratory University of California, Berkeley, October 1990)​

​

6 MOS6 (see T. Sakurai and A. R. Newton, A Simple MOSFET Model for Circuit Analysis and its application to CMOS gate delay analysis and series-connected MOSFET Structure, ERL Memo No. ERL M90/19, Electronics Research Laboratory, University of California, Berkeley, March 1990)​

​

8 BSIM3v3.3.0 from University of California, Berkeley as of July 29, 2005​

​

9 BSIMSOI3.2 (Silicon on insulator) from the BSIM Research Group of the University of California, Berkeley, February 2004.​

​

12 EKV 2.6 based on code from Ecole Polytechnique Federale de Lausanne. See http://legwww.epfl.ch/ekv and "The EPFL-EKV MOSFET Model Equations for Simulation, Version 2.6", M. Bucher, C. Lallement, F. Theodoloz, C. Enz, F. Krummenacher, EPFL-DE-LEG, June 1997.​

​

14 BSIM4.6.1 from the University of California, Berkeley BSIM Research Group, May 18, 2007.​

​

73 HiSIMHV version 1.2 from the Hiroshima University and STARC.​

​

According to the following document from Synopsys, Levels 6 and 7 are related but also have associated revision updates.

https://people.engr.tamu.edu/spalermo/ecen474/hspice_mosfet.pdf

See pp. 155-182

Man, that is a lot to swallow. It might even be above my pay grade. The solution to your problem seems to be use Level 6 or find another SPICE simulator that supports Level 7.

 

Hello,

I designed DVCC Instrumentation Amplifier with LTSPICE XVII. I used 0.18um Technology for FETs. The file is attached. When i simulate it i can take a good graph for DC characteristic but my frequency response seems wrong. Is there anyone who could help me. My Circuit and simulation results are attached.

Post your .asc file

 

That's two posts with the same request. Put all the files needed to run the simulation in a .zip file and help might be forthcoming. You should seriously consider compliance.

EDIT: 24 Hours and no files. I guess the TS has solved his own problem.