Hi!
I have what I thought was a success with a few weeks of operation, but failed

This part of the system uses a 4043B latch(Vdd 5V) to trigger a IRL540 mosfet to operate a solenoid valve that has a 3-4 ohm resistance and a 12V supply. Most of the time, the solenoid will only need to operate for a few minutes every 24 hours or so, but would like it to be able to operate for an hour or so from time to time.

It appears the failure was in the 4043B. For the conditions Q should have been high but appeared to be open.. I was able to trigger the mosfet by simply jumpering 5V to the gate. This led me to review the datasheet for the 4043 and question if I am requesting too much power from it to trigger the mosfet.

If I understand the datasheet for the 4043 correctly, Ioh would be the maximum current that can be supplied by the Q pin to the mosfet gate? From there it appears the maximum current this chip can supply to the mosfet is at worst 0.3mA, and at best 1mA??? My 1K pull down is going to pull 5mA plus the requirements of the mosfet's gate. Which, again, if I understand the datasheet correctly is more than the 4043 can supply.

So... am I understanding the datasheet to this point correctly?
If so, if I replace the 1K resistor with something like a 20K, would the system be reliable since now the current through the track would be 0.25mA? Is the 20K enough to ensure stability?
Is the pull down even necessary? On the datasheet it listed a sinking current. At first, I assumed when Q was not high it was floating(hence the pull down), but maybe without a pull down the 4043 has enough sinking current to prevent the mosfet from activating without a pull down?

Thanks for the help! Prototyped this on a solderable breadboard a few months ago, and after everything seemed good had PCB's made and ordered parts for a less hokey version. Was planning to build the boards tomorrow before I go out of town for a while, then saw the failure tonight. .

 

If I understand the datasheet for the 4043 correctly, Ioh would be the maximum current that can be supplied by the Q pin to the mosfet gate? From there it appears the maximum current this chip can supply to the mosfet is at worst 0.3mA, and at best 1mA??? My 1K pull down is going to pull 5mA plus the requirements of the mosfet's gate. Which, again, if I understand the datasheet correctly is more than the 4043 can supply.

I doubt that driving a MOSFET would damage the latch. I'd be more concerned about insufficient gate charging current causing the MOSFET to spend too much time in the linear region and causing increased power dissipation.

The 1k pulldown on the gate is unnecessary if you don't tri-state the latches.

 

am I understanding the datasheet to this point correctly?

Yes, a 1kΩ load is too much current for the CD4043 output.
You don't need any resistor if the 5V power is always there when the 12V power is on, as the CD4043 output will pull the output to 0V.
Otherwise a 20kΩ would be fine

 

Thanks a bunch both of you!
I guess out of habit when connecting these things to microcontrollers I just assumed that Q was either hi or floating and without the pull down I would have stability issues. I wont be tri-stating the latch, the enable pin is tied to vdd. Just you mentioning that though pointed to the error in my assumption.

Moot point now, but Dennis, you were probably correct regarding the linear region. I noticed that the MOSFET on my breadboard got VERY warm in operation(to which I chocked up to insufficient connections on the breadboard for the load). In fact, I assumed the failure was due to the mosfet until i probed the Q pin at a time the FET should be on, and got nothing. I was surprised to jumper the gate from the 5V rail and the solenoid operate. So I guess it did not build enough heat to fail the moset, but it if the latch survived the fet probably would have died at some point.

From here, can you guys help me wrap my head around something that I never really thought about, but this very low driving current from this latch has me thinking about? I'm essentially trying to understand what the gate current requirements are for this MOSFET(which until now, I assumed was negligible.

Seems like all the tutorials I have seen so far say they are voltage dependent, and that's it. But even at steady state, there has to be SOME current requirement.

And then there's the transient from off to on. I am assuming this is where the gate charge vs gate voltage chart, Ls, and Ciss(and maybe gfs) come into play? The gate has a certain capacitance and inductance, which when it goes high intially requires significantly more current? Then when switched off there is likely a similar spike going back to the driver, in this case a latch?

 

I'm essentially trying to understand what the gate current requirements are for this MOSFET(which until now, I assumed was negligible.

Seems like all the tutorials I have seen so far say they are voltage dependent, and that's it. But even at steady state, there has to be SOME current requirement.

The gate of the MOSFET looks like a capacitive load to the latch output. The small current from the output needs to charge the gate capacitance. The longer that takes, the longer it takes for the MOSFET to get to a low resistance ON state.

How significant that time is depends on, among other things, the load current being switched and the frequency that it's being switched.

 

In the steady-state a MOSFET gate draws only a very minute leakage current (usually specified in the data sheet).

 

Thanks again!
I am figuring the worst case is the period when the latch goes high and energizes the gate.
I have been researching this when I could today and looks like approximations for gate current are gate charge over time?
If that is a decent ballpark assumption, the rise time(tr) on the datasheet is 81nS. Using figure 6 and the 20v scale for Vds and a Vgs of 4.5v looks like gate charge is ~38nC?
38nC/81nS= 0.47A???

1) Is this even correct?
2) if so, in the future I suppose I should use a gate resistor inline between Q and the gate to limit current at the expense of rise time(not much of a concern since this is a non PWM application).
3) my current PCB does not have a way to put the resistor in. Will this current draw when Q goes high cause a very premature failure again of the latch?

 

If that is a decent ballpark assumption, the rise time(tr) on the datasheet is 81nS.

What datasheet?

NSC:



You're operating at 5V, transition time could be 200ns.

Intersil doesn't even give parameters for 5V:




But, since Intersil parts are meant to be compatible with all other CD4043, you could assume the NSC figure can be used.

 

Original post has pdf attachments to the datasheets of the components I'm using. The 81ns was from the mosfet. But I see that you are looking at the output of the latch, which makes sense. But even on the TI sheet it's still 100ns typ, 200 max.
If I'm right with the formula and gate charge of 38nC it's still .38A for a typical tlh?

 

That's the right ballpark, but for your application even a 1ms charge time would be insignificant, so you could use a gate resistor of several kΩ to keep the latch IC happy without prolonging the FET switching time unduly.