Hallo everyone! I have to check if the 8051 controller is able so source enogh current for a bus.There's ADC, AMUX, RAM, some 3-state latches conected to the address-data bus.I've found that 8051(AT89C51) can source IOHCPU= -25 µA
How to calculate how many current the bus needs? Is there just 5 HCT inputs and one HCT output(from ADC), or some high-impedance outputs/inputs connected to AD0:AD7 bus, that i need to add in my calculations?
here's the schematic http://www.ipix.lt/images/87572461.jpg
thanks.

 

You need to read the datasheet very carefully. The behavior of port 2 and port 0 is different when they are used as an address/data bus. As quasi-bidirectional I/O ports they have very limited ability to source current. Give me a link to a specific manufacturers datasheet and I'll try to help you sort this out.

CMOS inputs do not sink current like the inputs of the multi-emitter transistor in the old TTL parts. What they look like is a capacitative load. What you need to charge and discharge that load capacitance is current sourcing and sinking.

 

You need to read the datasheet very carefully. The behavior of port 2 and port 0 is different when they are used as an address/data bus. As quasi-bidirectional I/O ports they have very limited ability to source current. Give me a link to a specific manufacturers datasheet and I'll try to help you sort this out.

CMOS inputs do not sink current like the inputs of the multi-emitter transistor in the old TTL parts. What they look like is a capacitative load. What you need to charge and discharge that load capacitance is current sourcing and sinking.

i reffered to this http://www.qsl.net/yo5ofh/data_sheets/74xxspec.htm taking in mind that almost all devices connected to the bus are 74HCT family.

also the controller's datasheet :http://www.atmel.com/dyn/resources/prod_documents/doc0265.pdf (page 10)
If i made a mistake, judging about the family of each component here are their datasheets:
flip-flops 74HC377 http://calypso.inesc-id.pt/FCUL/inst/praticas/74hct377.pdf
address latch 74HC373 http://www.nxp.com/acrobat_download/datasheets/74HC_HCT373_3.pd
MUX http://www.analog.com/static/imported-files/Data_Sheets/ADG406_407_426.pdf (i think it's 74HC, right?)

RAM http://www.cs.uml.edu/~fredm/courses/91.305/files/cy6264.pdf
Should i treat RAM as an input, or high impedance output, or both?

 

On page 10 of the datasheet that you referenced are parameters VOH1 and VOL1 which are for Port 0 when it is used as the multiplexed address/data buss. What you notice from these figures is that port 0 will sink 2 TTL loads (3.2 mA) and it will source up to 800 uA while keeping the voltage above 2.4V with a VCC of 5V. The HCT parts have TTL thresholds so I think with 5 loads plus the RAM chip you will be fine at modest oscillator frequencies.

You might have problems if the board is large, and the traces are long, and the oscillator is 24 MHz. They might involve reflections from unterminated transmission lines or possibly excessive capacitative load.

One final warning. The datasheet is marked "not recommended for new designs". This is generally an indication that you should strongly consider the reommended alternative unless you have the parts in hand, or this is a one off design.