I would like to replicate the test performed in this video but using this gate driver.




I tried replacing their gate driver with mine but the simulation does not give expected results.
There are many parameters to set, some of which I may even overlook.

I usually see this test done on single mosfets ... but on the integrated gate driver I have difficulty and the only video that talks about it I think is the one I found.
So what I'm asking is, is this test useful in an integrated driver like EPC2152?
Because everything happens inside the chip, I cannot measure the gate current because the two inputs of the chip are "digital" and I don't have access to the gate. Am I wrong?



I'll send you the .asc file first and we'll comment on it together.


I don't understand in general what connections I need to make and what parameters to set because the topology of my gate driver is different from the one used in the example.
Other videos connect the input generator to the gate of the mosfet (low side or high side), but we are still talking about half bridge.



(I tried to attach the NET and text file of EPC2152 but they are not supported .. you first do download the template from the official site in my opinion)

 

Here is a modified version of your schematic with much of the extraneous stuff removed. The EPC2152 requires logic level inputs so I changed them to 0-3.3 V levels. I added a 0 V source to measure the driver's GND current, which is dominated by its lower FET current. I also added a cap on the output node to reduce the high voltage and high frequency ringing when the lower FET is turned off.
HTH

 

Here is a modified version of your schematic with much of the extraneous stuff removed. The EPC2152 requires logic level inputs so I changed them to 0-3.3 V levels. I added a 0 V source to measure the driver's GND current, which is dominated by its lower FET current. I also added a cap on the output node to reduce the high voltage and high frequency ringing when the lower FET is turned off.
HTH

Hi Dennis.
Thank you very much for your modifications, very kind.

I have some doubts I would like to ask you.


1) How come you get the current on the generator (blue curve) and not on the resistor (red curve) as in the video?

2) If I'm not wrong, those oscillations are characteristic of GaN. I would like to compare this test simultaneously with a gate driver with Silicon.
I tried to import one by also choosing of transistors with similar resistance to EPC2152.
I am sending you the file you sent me but with the addition of the new driver and I still kindly ask you to help me with the connections.
The idea is to get something like this:

 

Here is a modified version of your schematic with much of the extraneous stuff removed. The EPC2152 requires logic level inputs so I changed them to 0-3.3 V levels. I added a 0 V source to measure the driver's GND current, which is dominated by its lower FET current. I also added a cap on the output node to reduce the high voltage and high frequency ringing when the lower FET is turned off.
HTH

Just updated the .asc file in my previous post #3

 

1) How come you get the current on the generator (blue curve) and not on the resistor (red curve) as in the video?

2) If I'm not wrong, those oscillations are characteristic of GaN. I would like to compare this test simultaneously with a gate driver with Silicon.

Re 1), I used the 0 V source as an ideal amp meter to measure the current in the GND pin of the EPC2152 since there is no access to the internal FET's source current. I could have simply probed the current from the GND pin of the EPC2152 symbol, but I find the amp meter to be more obvious.

Re 2), No, those oscillations are due to the inductances and capacitances in the circuit. The low frequency oscillation is due to the load inductance and the load capacitance ringing when the low FET turns off. I added a load capacitance (in addition to the capacitance of the FETs) to reduce its frequency. Similarly, the high frequency oscillations are due to the bus inductor ringing with the small capacitance of the FETs or the Vin pin of the EPC2152.

I attached a revised schematic that adds a load resistance on the output to provide some damping to the load inductance oscillation, and a small bypass capacitor on the Vin (or FET high side supply) to eliminate the high frequency ringing due to the bus inductor.

BTW, you did not include the autogenerated symbol of the LM5109B in your upload. Autogenerated symbols are problematic because they refer to a path to the autogenerated folder on your computer. It's best to copy the symbol and model file to your schematic directory and then edit the symbol to remove the path to the model file. I did that with the autogenerated symbol I had to recreate.

 

I did not look at your data in detail. Many of the old gate drivers ate not good for GAN. They are too slow and cannot work at the low voltages required. (depends on which GAN)

 

Re 1), I used the 0 V source as an ideal amp meter to measure the current in the GND pin of the EPC2152 since there is no access to the internal FET's source current. I could have simply probed the current from the GND pin of the EPC2152 symbol, but I find the amp meter to be more obvious.

Re 2), No, those oscillations are due to the inductances and capacitances in the circuit. The low frequency oscillation is due to the load inductance and the load capacitance ringing when the low FET turns off. I added a load capacitance (in addition to the capacitance of the FETs) to reduce its frequency. Similarly, the high frequency oscillations are due to the bus inductor ringing with the small capacitance of the FETs or the Vin pin of the EPC2152.

I attached a revised schematic that adds a load resistance on the output to provide some damping to the load inductance oscillation, and a small bypass capacitor on the Vin (or FET high side supply) to eliminate the high frequency ringing due to the bus inductor.

BTW, you did not include the autogenerated symbol of the LM5109B in your upload. Autogenerated symbols are problematic because they refer to a path to the autogenerated folder on your computer. It's best to copy the symbol and model file to your schematic directory and then edit the symbol to remove the path to the model file. I did that with the autogenerated symbol I had to recreate.

I did not look at your data in detail. Many of the old gate drivers ate not good for GAN. They are too slow and cannot work at the low voltages required. (depends on which GAN)

Actually, now that I think about it, I notice that one of the most useful things of the Double Pulse Test is to monitor Vgs of the transistor when it switches, but in the EPC it is all integrated so I don't know how much use it can be this test. Am I wrong?
But anyway, just to finish the simulation, I'll attach the symbol I had forgotten.

Thanks for the help

 

I notice that one of the most useful things of the Double Pulse Test is to monitor Vgs

On any fast part you cannot really see what is happening inside. The length of the leads causes inductance. The PCB layout will change everything. I have been driving the Gates negative to help with ringing.

is this test useful in an integrated driver like EPC2152?

The integrated driver removes all the PCB-Gare-Drive layout problems. Or at least there is nothing you can do make it worse/better. If you have never fought with GAN PCB problems, you probably should look at integrated.

I have not used one of their integrated parts. I found the GANs to be very fast. 1.5nS switching is impressive. In the real world (not SPICE) it is hard to measure current with a bandwidth to see 1.5nS.