Hello,
In the datasheet there is a typical configuration given.
It clearly shows wich pins are input and wich are output:

Hello Bertus,
yes, we have yet concluded that output pins cannot absolutely share the same resistor. The remaining question is about input pins only.
Suppose that you have two input pins that must pulled to Vdd, would you use two resistors or just one?

 

Hello Bertus,
yes, we have yet concluded that output pins cannot absolutely share the same resistor. The remaining question is about input pins only.
Suppose that you have two input pins that must pulled to Vdd, would you use two resistors or just one?

While I see no obvious objection to shared input pull-ups - I'm bound to ask why you wish to vary from the manufacturer's advice? Is it a matter of limited PCB space?

Best regards
HP

 

Yeah, but what happens if the IC manufacturer states explicitly "Pull up to VDD via 100 kΩ resistor if unused." for those pins?

In the case of inputs build with the CMOS technology, the VDD supply bus carrying high dV/dt noises, this tends to not only make the port be unwanted activated, but in worst cases even burn it.

 

While I see no obvious objection to shared input pull-ups - I'm bound to ask why you wish to vary from the manufacturer's advice? Is it a matter of limited PCB space?

yes, also you're going to save a lot of manual soldering activity in case you have to do, let's say, 50 boards by yourself.

 

In the case of inputs build with the CMOS technology, the VDD supply bus carrying high dV/dt noises, this tends to not only make the port be unwanted activated, but in worst cases even burn it.

I'm lost... sorry...

 

yes, also you're going to save a lot of manual soldering activity in case you have to do, let's say, 50 boards by yourself.

Sounds as if you're contemplating manufacturing? In which case your underwriters will thank you for following 'the book' to the letter - necessary or not!

Best regards
HP

 

I'm lost... sorry...

Succinctly; noise on the Vdd rail may falsely trigger or damage directly connected inputs -- latchup is also a concern...

 

Succinctly; noise on the Vdd rail may falsely trigger or damage directly connected inputs -- latchup is also a concern...

So connected input pins can put the transistors in a potential latch-up situation when/if power goes close to zero? I think that this close the question. The risks are too high if compared to manufacturing benefits.

 

So connected input pins can put the transistors in a potential latch-up situation when/if power goes close to zero?

In the interests of completeness, I'm bound to point out the fact that the above referenced risks apply only to inputs tied to the Vdd rail -- Please note that it's not about 'swinging too near ground' but, rather, noise/hash exhibiting over-rapid transition times with consequences analogous to "ΔV/Δt switching" of thyristors ...

The risks are too high if compared to manufacturing benefits

Generally speaking, I share that sentiment as regards failure to observe manufacturer's application literature!

Best regards
HP