Just for grins, here's my test circuit with the supply voltage at zero, which shows no Miller plateau in the gate voltage, as expected.

 

So are you measuring the current and voltage going to the drive circuit to determine its power?

I haven’t got around to that yet, so I am still measuring just the input power at the bench top power supply which was around 2.5W. But this is substantially higher than what would be expected from the 1.37W that we calculated should be dissipated from charging and discharging the capacitance.

However the power dissipation that was experienced when using the actual gate drive IC was only slightly lower than that which I observe with the totem pole driver.

This was what initially caused my confusion, I noticed that my equations, rise and fall times, etc all agreed with a charge per cycle of somewhere in the region of 1330nC, but when calculating the capacitor charge, I realised it was around half the actual gate charge required per cycle. So in my head I’m thinking, where on earth are all these extra losses coming from?!

Thanks for your help thus far, by the way, your feedback always proves helpful.

 

Just for grins, here's my test circuit with the supply voltage at zero, where shows no Miller plateau in the gate voltage, as expected.

View attachment 300789

Interesting, thank you, I’ve never actually seen the Miller effect in my simulations. I’m not sure if the models I’ve been using haven’t got it modelled… I’ll give this a go over the weekend.

 

I’ve never actually seen the Miller effect in my simulations. I’m not sure if the models I’ve been using haven’t got it modelled…

What simulator and models are you using?
Certainly all Spice models show show that.

 

What simulator and models are you using?
Certainly all Spice models show show that.

I use LTSpice mainly. I’ll have a go again tomorrow and focus on Miller pleateu.

what I still don’t understand, then, is if it takes 1330nC of charge to bring the FET into conduction, it surely takes 1330nC to bring it back out of conduction - so why do the formula typically state that gate driver loss is:

Qg * FSW * Vdiff?

Surely the total power dissipation should include both the ON gate charge and the gate OFF charge. So in my application I should expect the power dissipation of my driver to approximately double when connected to the actual FET of the total gate charge required is twice.

I suppose the dissipation won’t actually be twice, because during the Miller period the gate charge value is a bit lower than this and it occurs at a small gate-source voltage -so the power dissipation during this period is small. But I guess inserting a capacitance equivalent to the total gate charge is still the best way to go to get an idea of the average power dissipation during the switching period.

 

what I still don’t understand, then, is if it takes 1330nC of charge to bring the FET into conduction, it surely takes 1330nC to bring it back out of conduction - so why do the formula typically state that gate driver loss is:

Qg * FSW * Vdiff?

That is the energy that it takes to move that amount of charge, and after the charge has moved into and out of the gate, all the energy has been dissipated in the driver.
Why does that not seem correct to you?

 

That is the energy that it takes to move that amount of charge, and after the charge has moved into and out of the gate, all the energy has been dissipated in the driver.
Why does that not seem correct to you?

Because the data sheet and all application notes say that this is the charge (1330nC) to charge the effective gate capacitance - not to discharge it.

I am not saying it doesn’t seem correct, I’m absolutely sure it is - I’m just trying to get my head around why it is the case.

As your reply states “and out of the gate” this is my fundamental misunderstanding - surely it takes energy to pull charge out of the gate, which should be equal to the energy it takes to pump charge into the gate? The gate-source voltage to gate charge diagrams also seem to show only a positive going gate source voltage and it’s relation to gate charge, but I cannot see any relationship for the turn-off event and how much charge must be pulled out of the gate. Doesn’t the Miller capacitance effect turn off as well as turn on?

 

Because the data sheet and all application notes say that this is the charge (1330nC) to charge the effective gate capacitance - not to discharge it.

The implication is that they are the same, since any charge that goes into the gate has to also go out of the gate based upon the conservation of charge theorem (which I assume you understand), and the fact that there is nowhere else for the charge to go.

As your reply states “and out of the gate” this is my fundamental misunderstanding - surely it takes energy to pull charge out of the gate,

Ah no, surely it doesn't.
That appears to be the crux of your misunderstanding.
You don't need to "pull" the charge from the gate.
Certainly it requires energy to charge the gate capacitance, which leaves energy on the capacitance.
But since removing the charge just requires providing a path to ground (0V), then the energy from the charge is providing the movement of charge to ground, which is dissipated in the resistance to ground.
No other energy is involved in removing the charge.
I know you stated the off gate voltage is -4V, but that is not needed (and usually not used) to discharge the gate capacitance.

Doesn’t the Miller capacitance effect turn off as well as turn on?

Of course.
When the MOSFET turns back off, the Miller charge is returned to the gate where it is part of the charge going to ground.
See the Miller plateau during both turn-on and turn-off below:
And note that the positive charge current through R2 during turn-on equals the negative current during turn-off (purple trace).

Does all that make more sense now?

 

The implication is that they are the same, since any charge that goes into the gate has to also go out of the gate based upon the conservation of charge theorem (which I assume you understand), and the fact that there is nowhere else for the charge to go.
Ah no, surely it doesn't.
That appears to be the crux of your misunderstanding.
You don't need to "pull" the charge from the gate.
Certainly it requires energy to charge the gate capacitance, which leaves energy on the capacitance.
But since removing the charge just requires providing a path to ground (0V), then the energy from the charge is providing the movement of charge to ground, which is dissipated in the resistance to ground.
No other energy is involved in removing the charge.
I know you stated the off gate voltage is -4V, but that is not needed (and usually not used) to discharge the gate capacitance.
Of course.
When the MOSFET turns back off, the Miller charge is returned to the gate where it is part of the charge going to ground.
See the Miller plateau during both turn-on and turn-off below:
And note that the positive charge current through R2 during turn-on equals the negative current during turn-off (purple trace).

Does all that make more sense now?


View attachment 300826

Arghhh! Okay I’m finally following. Thanks for clicking on to what I was misunderstanding. One final thing, though (see attached).

The gate charge from gate to source and from gate to drain correspond to the charge of the input capacitance. However, the sum of these two quantities do not equal the total hate charge required to turn the device on. Why?! This is my assumption:

Driver supplies enough energy to being the gate source voltage to the Miller plateau, this is the QGS. The driver then supplies QGD to bring the device into conduction overcoming the Miller plateau. The remaining charge is provided by the driver to bring the gate source voltage to the final 15VDC. I would assume then, that the total charge should equal QGD plus QGS, with the actual gate source charge being the total charge minus that taken to overcome the Miller Plateau.

is there some other explanation for where that additional charge comes from?

 

the total charge should equal QGD plus QGS, with the actual gate source charge being the total charge minus that taken to overcome the Miller Plateau.

You have it reversed.
The Miller plateau is when extra charge is being provided to the input to supply that added by the Miller effect, and the voltage rise flattens due to the current through the source resistance (here 50Ω). With a zero source resistance the Miller voltage plateau would disappear.

The Miller effect increases the charge needed to charge the gate by a factor proportional to the voltage change on the drain terminal, so the total charge is that from the gate capacitance plus that from the Miller effect.
For example, if the drain voltage changes by 10V, then the voltage change across the gate-drain capacitor is now 10V plus the change in gate voltage (note that the two voltages are going in opposite directions), thus increasing the charge on that capacitor and the total charge needed to generate the ON gate voltage.

If you eliminate the Miller effect by setting the MOSFET drain to 0V, then the charge transferred should equal that required to charge and discharge the stated gate capacitance from the gate-source and gate-drain capacitances.

Are we on the same page now?

 

You have it reversed.
The Miller plateau is when extra charge is being provided to the input to supply that be added by the Miller effect, and the voltage rise flattens due to the current through the source resistance (here 50Ω). With a zero source resistance the Miller voltage plateau would disappear.

The Miller effect increases the charge needed to charge the gate by a factor proportional to the voltage change on the drain terminal, so the total charge is that from the gate capacitance plus that from the Miller effect.
For example, if the drain voltage changes by 10V, then the voltage change across the gate-drain capacitor is now 10V plus the change in gate voltage (note that the two voltages are going in opposite directions), thus increasing the charge on that capacitor and the total charge needed to generate the ON gate voltage.

If you eliminate the Miller effect by setting the MOSFET drain to 0V, then the charge transferred should equal that required to charge and discharge the stated gate capacitance from the gate-source and gate-drain capacitances.

Are we on the same page now?

So the total charge, 1330e-9, is equal to:

The charge required to charge CGD, CGS, and the charge required to get over the Miller plateau? So I guess the point is because I’m modelling just a capacitance with half the total gate charge, I am not taking into account the additional energy needed to overcome the Miller effect which is why the total gate charge needed is almost twice as much as that dictated from the total input capacitance alone.

If I am correct, then yes we are on the right page (fingers crossed!!)

 

If I am correct, then yes we are on the right page

I believe we finally are.

 

I believe we finally are.

Woohoo! Amazing. I knew there was something that just wasn't clicking. Thanks again for all your time and patience.

 

Any input as to why my BJT totem pole is dissipating so much power than would be dictated by the delta_VGS * QT * FSW equation? It is almost twice as much. I’m afraid if I solder in a capacitor twice as large, the power dissipation will double and exceed my maximum power supply power.

 

Any input as to why my BJT totem pole is dissipating so much power than would be dictated by the delta_VGS * QT * FSW equation? It is almost twice as much. I’m afraid if I solder in a capacitor twice as large, the power dissipation will double and exceed my maximum power supply power.

Show the circuit schematic and how you are measuring the power.
Otherwise I can only guess why.

 

Show the circuit schematic and how you are measuring the power.
Otherwise I can only guess why.

Attached is extremely similar to the circuit I am using. I am using a TI isolated gate driver and then the Nexperia PNP/NPN pair as shown in the schematic. The gate drive supply is +15V/-4V.

I am only measuring the input power consumed by my 12VDC bench top supply - but the isolated gate drive power supply I am using is at worst 80% efficient across the load power range. Although there’s going to be some error it should give me a good idea of what is being dissipated in the totem pole, because the actual TI driver will dissipate much less power as it only drives the base capacitance of the BJTs with a current somewhere in the region of ~1A. So I would expect the majority of the power dissipation to be within the BJT pair themselves.

 

You need to measure the actual +20V and -4V currents to get an accurate value for the power being used.
I don't trust the measurement of the input power of the bench power supply as giving an accurate indication of the driver power consumption.

 

You need to measure the actual +20V and -4V currents to get an accurate value for the power being used.
I don't trust the measurement of the input power of the bench power supply as giving an accurate indication of the driver power consumption.

I measured the input current with my multimeter - on DC mode it reads the same current as the DC power supply, however when switched to AC current mode the value is halved. This seems to explain the discrepancy, but that’s up with that? Is that a common thing?

 

it reads the same current as the DC power supply, however when switched to AC current mode the value is halved. This seems to explain the discrepancy, but that’s up with that? Is that a common thing?

Depends upon what the waveform looks like that you are measuring.

 

Can you post a diagram of exactly how you are measuring the current in your circuit?