In the model supplied by Diodes Inc for their DMG1016UDW, a paired N+P transistor package, their .subckt definitions look like:
*N-CH
.SUBCKT DMG1016VN D=10 G=20 S=30
* TERMINALS: D G S
I've emphasized the part I'm wondering about. In LTSpice, this syntax seems to not be supported and causes an error about too many external pins in the subckt. I see that Diodes Inc intends is to use the internal net names 10, 20, and 30 in the rest of the file, and they seem to be using D=10 to match the default MOS symbol's "D" pin to their internal "10" node. My question is twofold: what is this pin/node "aliasing" called, and what SPICE simulators support it since apparently LTSpice doesn't?
*N-CH
.SUBCKT DMG1016VN D=10 G=20 S=30
* TERMINALS: D G S
I've emphasized the part I'm wondering about. In LTSpice, this syntax seems to not be supported and causes an error about too many external pins in the subckt. I see that Diodes Inc intends is to use the internal net names 10, 20, and 30 in the rest of the file, and they seem to be using D=10 to match the default MOS symbol's "D" pin to their internal "10" node. My question is twofold: what is this pin/node "aliasing" called, and what SPICE simulators support it since apparently LTSpice doesn't?