Hey Guys,
I want to interface digital gray code encoder with micro controller. It has 5 digital input to be sensed with micro controller.
I want put micro controller in low power /standby/sleep mode when it is not in use.
So condition here is when user is rotate encoder from any position to any other position the micro controller should wake up.
Regards,

 

How you do this depends on what things can wake up whatever microcontroller you are using.

 

You could use the output of a one-shot, triggered by any transition of the 5 encoder outputs, to signal the micro to turn on.

 

Can you wake up the controller in time?
How fast are the input-changes?

 

You could use the output of a one-shot, triggered by any transition of the 5 encoder outputs, to signal the micro to turn on.

Hey,
Thanks for reply.
Could you please elaborate more about this ?

 

Could you please elaborate more about this ?

LTspice simulation of an example circuit below:

The U2 XNOR gate configuration generates a short (determined by the RC value) negative going pulse (blue trace) for each encoder output transition (green trace).
(If you need an explanation of that, I can further elaborate).

There are five CD4077 XNOR resistor-capacitor circuits, one for each encoder output (only one shown) that are connected to inputs 1 through 5 of the U1 8-input CD4068 gate (requiring two quad XNOR IC's)
(The 4 other inputs are tied high here for simulation purposes).
(V2 simulates the encoder output. I assumed that is a logic level signal.)

Thus the logic function of U1 (which acts as an OR/NOR function for the normally-high inverted pulses from the XNOR gates) causes the pulse output from any of the 5 encoder outputs to appear as a pulse at U1's output (red trace is negative polarity, and yellow trace is positive polarity pulse).

V1 (Vdd) is the logic supply voltage and can be anywhere between 3V to 15V.

Will that do what you want?

 

LTspice simulation of an example circuit below:

The U2 XNOR gate configuration generates a short (determined by the RC value) negative going pulse (blue trace) for each encoder output transition (green trace).
(If you need an explanation of that, I can further elaborate).

There are five CD4077 XNOR resistor-capacitor circuits, one for each encoder output (only one shown) that are connected to inputs 1 through 5 of the U1 8-input CD4068 gate (requiring two quad XNOR IC's)
(The 4 other inputs are tied high here for simulation purposes).
(V2 simulates the encoder output. I assumed that is a logic level signal.)

Thus the logic function of U1 (which acts as an OR/NOR function for the normally-high inverted pulses from the XNOR gates) causes the pulse output from any of the 5 encoder outputs to appear as a pulse at U1's output (red trace is negative polarity, and yellow trace is positive polarity pulse).

V1 (Vdd) is the logic supply voltage and can be anywhere between 3V to 15V.

Will that do what you want?

View attachment 291661

Hey C,
Thanks for your time.
Yes, that is similar i was trying to think.
Let me explain you more detail. My encoder is absolute gray code that means one output will change at a time e.g. all high 1 1 1 1 1 ->1 1 1 1 0 and 1 1 1 0 1 etc.
You can see in my circuit i will reading the encoder output by using microcontroller input pin.
Ideal state -> 1and when encoder turned ON 0
11111
11110
like that.
So this my understanding !
My problem is not about sensing encoder input as you can see in my drawing.
I am more worried about when my microcontroller is in sleep mode/deep sleep mode/Low power/standby etc. if user turn knob of encoder microcontroller has to be wakeup.
1 encoder has 5 gray code output
so i have 4 encoder that means 20 combination (let us assume user can turn any encoder out of 4).
So here i was thinking to have one e.g. high to low external interrupt signal which wakes up microcontroller. I can do it by software wakesup e.g. wakeups all 20 pin microcontroller periodically and monitor input pin status but this will incease controller power consumption so i do not want this approach.
Hope this will give you more insight !
Any idea is highly welcome !
Thanks, m

 

1 encoder has 5 gray code output
so i have 4 encoder that means 20 combination

All I can think of is to use my circuit with 20 XNOR circuits connected to 3 daisy-chained AND/NAND gates to give one wake-up pulse whenever any decoder output changes state.
That would require five XNOR ICs and three 8-input AND/NAND ICs.
Those circuits draw only the negligible IC leakage current when static.

You could likely eliminate the 100nF capacitor in the XNOR circuit while increasing the input resistor to 1MΩ to reduce the required discrete components to only one per XNOR gate.
With the typical stray IC input capacitance of 5pF (not including any added wiring trace capacitance), the output pulse should be at least 5µs.
If that's not sufficient to trigger the micro wakeup, the pulse could trigger a one-shot at the last AND/NAND output for a longer pulse.

Sound feasible?

 

All I can think of is to use my circuit with 20 XNOR circuits connected to 3 daisy-chained AND/NAND gates to give one wake-up pulse whenever any decoder output changes state.
That would require five XNOR ICs and three 8-input AND/NAND ICs.
Those circuits draw only the negligible IC leakage current when static.

You could likely eliminate the 100nF capacitor in the XNOR circuit while increasing the input resistor to 1MΩ to reduce the required discrete components to only one per XNOR gate.
With the typical stray IC input capacitance of 5pF (not including any added wiring trace capacitance), the output pulse should be at least 5µs.
If that's not sufficient to trigger the micro wakeup, the pulse could trigger a one-shot at the last AND/NAND output for a longer pulse.

Sound feasible?

Hey C,
Again thanks for time and helping me out.
I am still trying to figure out what you said, sorry for lack of knowledge.
let me explain what i understood from your post.
lets say gray code output -> 00001
so 5 XNOR gate output -> 1111(0) , zero in bracket will be for only RC time constant (47K, 100nF) and then after RC output will be -> 11111
Output of AND gate -> 0 for RC time and then it will become high after RC
During this time uC will read interrupt signal and wakes up.

Since you said 3 daisy-chained AND/NAND gates, Could you please explain me more about how todo daisy-chaining of 3 AND/NAND gates.
Thanks again !

 

lets say gray code output -> 00001
so 5 XNOR gate output -> 1111(0) ,

Not sure what you mean by your notation.
All XNOR outputs stay at a logic 1 when all the decoder outputs are static (either 1 or 0), so a static 00001 or any static code combination from the decoder generates 11111 from the 5 XNOR gates.
That's because an XNOR gate has an output high when both inputs are 0 or both inputs are 1.
The output is low only when the two inputs are different.
This occurs only when any one of the encoder outputs changes state, either 0 to 1 or 1 to 0, and the XNOR inputs are different for a short time due to the RC delay.

Could you please explain me more about how todo daisy-chaining of 3 AND/NAND gates.

There are 20 XNOR outputs going to the three 8-input AND/NAND gates, leaving a total of 4 spare inputs.

• Connect the XNOR outputs such that AND/NAND gates two and three have one spare input.
• Connect the /Out of the first, to the spare input on the second, and the /Out of the second to the spare input of the third.
• The 2 outputs of the third are the wake-up signal pulse. Pick the one with the desired pulse polarity.
• Make sure and tie the two remaining spare inputs on the first AND/NAND to the power supply (logic 1).

All make sense?

 

Not sure what you mean by your notation.
All XNOR outputs stay at a logic 1 when all the decoder outputs are static (either 1 or 0), so a static 00001 or any static code combination from the decoder generates 11111 from the 5 XNOR gates.
That's because an XNOR gate has an output high when both inputs are 0 or both inputs are 1.
The output is low only when the two inputs are different.
This occurs only when any one of the encoder outputs changes state, either 0 to 1 or 1 to 0, and the XNOR inputs are different for a short time due to the RC delay.
There are 20 XNOR outputs going to the three 8-input AND/NAND gates, leaving a total of 4 spare inputs.

• Connect the XNOR outputs such that AND/NAND gates two and three have one spare input.
• Connect the /Out of the first, to the spare input on the second, and the /Out of the second to the spare input of the third.
• The 2 outputs of the third are the wake-up signal pulse. Pick the one with the desired pulse polarity.
• Make sure and tie the two remaining spare inputs on the first AND/NAND to the power supply (logic 1).

All make sense?

Hey C,
Fully aligned.
Thanks for your time !