Hello,
I have made a simple small circuit for my company. It is used to measure and report whether or not a batteries terminal voltage is within a nominal range. I have 20 boards connected to a battery stack in house here. The circuit seems to run fine, but after a few days, the boards starts to fail --kinda--. The failure is intermittent and many times only manifests itself when attached to a battery. It's difficult to observe the problem on the bench. The problems take the form of timing and logic error from the CMOS digital ICs. I don't have problems with the optocouplers or comparators. The CD4049UB(inverter) is the worst. It seems to fail most frequently.

What could be the problem? The battery stack is connected to a battery charger. All the batteries are in series. The batteries are 12.5V each. Is it just bad practice to attach CMOS to a battery stack where the VDD, VSS with respect to earth ground can be as high as 600V?

I along with my colleges are baffled. The boss says the problem is that all the boards are in series along with the batteries. I asked him to elaborate more, but he couldn't. Whatever he thinks is the problem, he thinks doesn't require more explanation.

The board schematic is attached, and layout. Is it possible that a batch of board can just be flakey?

 

I want to add a little more. The upper left connector is the battery terminal, and the six pin connectors are for a clock, token and flag. The clock propagates the token. The token determines whether a board should propagate its flag or carry on the given flag. The flag is whether or not the battery voltage is in range.

 

Just a couple of thoughts.

I don't see anything to limit the current to the optos by R1 and R2. Maybe it is on the other part or maybe the resistors are drawn wrong?

You might add some decoupling to the supply lines, could be some noise.

It looks like the optos protect you from the 600 volts and the boards just kind of float there on their own battery?

Could it be the charger voltage goes above 15 volts?

 

Very good observations.

The boards will be connected from the 6pin connector on the left to the 6pin on the right.
The resistors to limit the current are there.

Bypass caps are are interesting idea, but I must stress the components are failing. And the circuit runs at 1-10hz.

You are right the board just floats.

I guess it is possible the charger gets high. I will investigate that. Where did you get the 15 volt number? My impression is that these components will easily tolerate 18 volts. The charger is Dependant on the input line ac. It cannot exceed 15.5v unless the commercial power surges considerably.

 

Oh, you mean failing as in broken?
In that case it almost has to be something with the battery voltage as everything else is isolated with the optos.
Your right 18 volts on the CD logic 20 volts absolute maximum.
So is this like 50 lead acid batteries in series?
My bet at this point would be a transient on the battery voltage. Can you scope it?

 

Oh, you mean failing as in broken?

That's the crazy thing. I know the ic changes. I know it doesn't respond how it did when I installed it, but its very hard to pin down on account of how intermittent the failure is and how less likely the failure is to appear when taken out of the system.

In that case it almost has to be something with the battery voltage as everything else is isolated with the optos.

The boards themselves monitor the battery voltage and they have only reported one battery being over 15 volts that however wasn't where the failure is. Perhaps it is a very short transient?

Your right 18 volts on the CD logic 20 volts absolute maximum.
So is this like 50 lead acid batteries in series?

Yep. Our company sells ups

My bet at this point would be a transient on the battery voltage. Can you scope it?

I'll give it another look.

 

Oh, you mean failing as in broken?

That's the crazy thing. I know the ic changes. I know it doesn't respond how it did when I installed it, but its very hard to pin down on account of how intermittent the failure is and how less likely the failure is to appear when taken out of the system.

In other words it is ok again on the bench after a failure?

How does the failure manifest itself?

 

Oh, you mean failing as in broken?

In other words it is ok again on the bench after a failure?

How does the failure manifest itself?

Most times it is OK after a failure on the bench. A small portion of them still fail on the bench after being taken out of the system and then its intermittent. I had one where there was a delay in the inverter of about three seconds. The input changed, but the output wouldn't change for so long.

The failures in the system manifest as time delays and faulty output states for the respective input state. For instance if pins 3,4 on the left are active then pins 3,4 on the output will be active on the right. This shouldn't be. They are delayed by the clock and the flip-flops, but after one week of successfully delaying this signal with respect to the clock it now will not delay it in the system, but it still does on the bench.

To clarify there are two delays o speak of. On is the proportion delay of the gate which should not be as long as it gets. Another delay is a function of the board which it is designed to do, by the flip flop.

 

<rant> First off, find the guy who drew the schematic and fire him… or give him a course in basic layout. A good schematic tells a story using “just the facts.” It does not hide details, it preferably flows left to right, wires are evenly spaced, ground is at the bottom (or center in a dual supply circuit), and most definitely wires NEVER run thru other parts the do not connect to. </rant>

What does “failure” mean? Functional failure or a hard failure where parts need replacement?

Which 4049 fails? Which one (or more?) of 6 sections?

 

What does “failure” mean? Functional failure or a hard failure where parts need replacement?

It's a hard failure.

Which 4049 fails? Which one (or more?) of 6 sections?

Thats a good question. Most times when I get it back to the bench I can nolonger observe the failure, so I can't figure out which section. I'd say IC5 is the most frequent, followed by IC3 then IC4 I've never seen the flipflop(IC2) optocoulpers or comparators to fail.

I took a look at the ripple from the charger again. Its only 10mV. maybe some crazy event occurs and it spikes, I cannot look at it forever.

 

Hello,

I do not see any decoupling capacitors on your PCB and schematic.
Decoupling capacitors will prevent the pulses to "walk" on the powerlines and cause erratic operation.
Here is a thread that will tell you more:
Decoupling or Bypass Capacitors, Why?

Bertus

 

Hello,

I do not see any decoupling capacitors on your PCB and schematic.
Decoupling capacitors will prevent the pulses to "walk" on the powerlines and cause erratic operation.
Here is a thread that will tell you more:
Decoupling or Bypass Capacitors, Why?

Bertus

It is good house keeping to include bypass capacitors, but you need understand why they are unnecessary here.

1. The ripple on the supply is 10mV from the charger
2. The battery is a 40F capacitor with only .005ohms source impedance and is the source
3. the logic transition @5Hz

there is little reason to put capacitors where there is no AC and the source is already so stiff(a car battery).

If I put a cap on the board I'd have 40F(battery) + .00001F(electrolytic) = why even bother?

 

I would agree with the boss. Not sure why.

With the high voltage series circuit, a few ms of high impedance, in one section, due to connections or chemistry, might be bad.

A 20 or 30 volt mov across each stage?

Can you explain the board power supply circuit?

edit:

"there is no AC and the source is already so stiff"
Noise and ac are everywhere!

 

I would agree with the boss. Not sure why.

I do.

With the high voltage series circuit, a few ms of high impedance, in one section, due to connections or chemistry, might be bad.

A 20 or 30 volt mov across each stage?

Can you explain the board power supply circuit?

The board is connected with the two pin connector in the upper left being connected to the battery terminals. The batteries are 12volt car batteries. There are many batteries, with boards connected to them, in series.

edit:

"there is no AC and the source is already so stiff"
Noise and ac are everywhere!

I just got done measuring it. The supply is 10mV max ripple/noise when the clock running. The batteries are inside a metal cabinet. there is very little noise. I would also assert a car battery is one of the stiffest source you can find.

 

Mmmm, Take your pain killers, cause this is gonna hurt.

Hopefully it's all on one board and powered by one battery!

It sounds like latchup which CMOS is famous for.

http://www.fairchildsemi.com/an/AN/AN-600.pdf

While the battery is a stiff source the wires to the board may not be if they are very long at all. The easiest would be to try the decoupling. Maybe .1 or .01Ufd at least each inverter and maybe an electrolytic across the connector.
The other altenitive would be to build say a 15 volt supply with a resistor and zener and a filter cap to run everything that touches the CMOS.

 

Mmmm, Take your pain killers, cause this is gonna hurt.

Hopefully it's all on one board and powered by one battery!

It sounds like latchup which CMOS is famous for.

http://www.fairchildsemi.com/an/AN/AN-600.pdf

It's an interesting article. It will take me some time to judge whether this is what I am experiencing.

While the battery is a stiff source the wires to the board may not be if they are very long at all. The easiest would be to try the decoupling. Maybe .1 or .01Ufd at least each inverter and maybe an electrolytic across the connector.
The other altenitive would be to build say a 15 volt supply with a resistor and zener and a filter cap to run everything that touches the CMOS.

the wires are 1 foot long at 18AWG. The resistance of a wire such as this is .006 ohms. The nominal equivalent resistance of a electrolytic is @1ohm.

The capacitor is redundant. The battery is 40Farad with .005ohm impedance the capacitor is .000001Farad at 1Ohm impedance. It will be like the cap isn't even there.

the ceramics are about .015ohms impedance which is still higher or equal to the battery impedance + wires. I still gain nothing by adding caps. The battery is sufficiently stiff.

Regardless I have measured the rails and they are under 10mv noise. Empirically, I know I don't have a noise problem.

 

It's not the resistance, it's the inductance. Two feet of wire looks like 125 ohms at 100Mhz (edge frequency). Try it on the bench with 3 or 4 feet of wire going to the power supply while feeding the logic something to make it switch. They will be very short spikes, but maybe it will fail.

 

It's not the resistance, it's the inductance. Two feet of wire looks like 125 ohms at 100Mhz (edge frequency). Try it on the bench with 3 or 4 feet of wire going to the power supply while feeding the logic something to make it switch. They will be very short spikes, but maybe it will fail.

I imagine the edge would be degraded, but the clock runs at 5Hz. The signal has 0.1seconds to reach its level. I'm not very worried about slew rates, timing, noise. What bothers me most is the physical change that occurs that renders the IC unusable in the machine. The wire length between the test fixture on the bench and the ones in the machine are approximately the same. In the machine I can get 50% fail and on the bench it's 0% for the last failure case. I changed the IC(IC3 CD4049UB) and it doesn't fail at all now. Unfortunately, this keeps happening. Everyfew days, a board will begin to fail. I'll fix it, then it will be fine for a few days, until another one flakes out.

 

Sorry, I didn't put that very well. It's not the speed of the edges it is the inductive kick you get from the logic transitions. Here is a simulation with .2 Uh in the power lead. (about what you get with 2 feet of wire) While these things don't model well you can see from the 2 circuits that without the decoupling cap the voltage goes pretty high. I could be wrong, but I think if you try it you will like it.
It's not like there is anything else that can do it.

 

Sorry, I didn't put that very well. It's not the speed of the edges it is the inductive kick you get from the logic transitions. Here is a simulation with .2 Uh in the power lead. (about what you get with 2 feet of wire) While these things don't model well you can see from the 2 circuits that without the decoupling cap the voltage goes pretty high. I could be wrong, but I think if you try it you will like it.
It's not like there is anything else that can do it.

Th voltage doesn't go pretty high. I've measured it many times. The vcc is fine. Also the vout from the inverter doesn't look like that. There is no ringing. The rise and falls are critically damped. There is something wrong with the simulation. I accept a capacitor could help if those problems were real, but ringing is not showing up on the scope, and a capacitor couldn't make it vanish completely if they were there.