Detect and react to high impedance state of LVDS line

Thread Starter

LordOfThunder

Joined Jun 27, 2018
80
You need to be very careful,
LVDS outputs are current outputs, CML, not voltage
the voltage range of an output is there to specify what voltage range the current source / sinks of the LVDS output is compliment.
Thats why you need the 100 ohms across the + - of the pair to receive a voltage .

NAND gates,
depending what you select, can source / sink current that is noticable compared to the small current change that LVDS uses to indicate '1' or '0.

BTW,
at the transmitter,
how are you making the + and - output of a LVDS '1' at the same time,


At the speeds of a "RS232" link,
one of the "failsafe" circuits might be if use,

https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3662.html

https://www.ti.com/lit/pdf/slla082

https://www.ti.com/lit/an/snla051c/snla051c.pdf

You can safely put a second LVDS receiver across an input,
and use this output as the fail safe,
Thank you very much for the wealth of information about LVDS. I more or less understand what are your concerns and I will try to address them.

I have no access to the transmitter design, so I do not know how the LVDS line is going to be driven to high-impedance. I was going to put two weak pull-down resistors on the LVDS outputs in order to drive them to ground in case of high-impedance state.
 

Deleted member 115935

Joined Dec 31, 1969
0
putting any resistors at the transmitter is not a good idea

if the LVDS receiver is not powered, then you have no definition as to what its impedance is,
You also need to check what the input voltage limits are on the receiver with no power applied,

Not starting form here syndrome,.
hind site and all that.....

If you had used AC coupled LVDS,
and then encoded the RS232 with say Manchester,

where your at,
sorry, not much of an answer with minimum change,
may be those pdfs on fail safe have an answer ? I knew they were there but only managed to skim them.
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
80
I do not like the idea of putting pull-down resistor to the LVDS lines too. However, notice that I am putting those resistors on the receiver end. As I said the transmitter end is out of my reach.

Yes, those PDFs are a good reference. I have skimmed through them. It seems that our LVDS receiver (SN65LVDS4) requires an external failsafe.
 
Last edited:

Deleted member 115935

Joined Dec 31, 1969
0
note if your receiver does need a fail safe set of resistors, and they arnt there,
then the receiver can easily oscillate on its own ,
I had one about 20 Mhz, which was unfortunate as that was the clock we were expecting !
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
80
I have simulated both of the circuits proposed in this thread. The one using two comparators and the one using a logic gate. They both seem to work satisfactorily. I personally prefer the one using two comparators because more robust against common-mode offsets.

In any case, both of the LVDS wires need to be pulled up or down. I have confirmed that the influence of the pulls is negligible if the pull resistors are in the order of 10k~50k Ohm, by checking the current over the termination resistor (3.5mA) against the current over the pulls (20~50 uA). However the logic gate solution introduces significant noise upon switching (not sure if it is just a glitch in the simulation though).

The only real drawback of these two designs is that I must give up the failsafe features because in case of line disconnect/short/high-impedance the LVDS wires are pulled down or up and the receiver can switch because of random noise. This probably is not a critical issue because the whole point of this mental exercise is to shut down the device if the LVDS connection is compromised or voluntarily put into high-impedance mode.
 
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