Detect and react to high impedance state of LVDS line

Thread Starter

LordOfThunder

Joined Jun 27, 2018
67
Hello!
The following is a kind of mental exercise that I am trying to solve.
Let us assume that a circuit like the one below, where there is a power line powering a DCDC converter and a load. By load, I mean a generic complex circuit with computing power and so on. There is also a reset line whose only purpose is to carry a reset signal whenever the power to the load should be cut or restored. A dedicated switching circuit reads the reset signal and switches the power accordingly. Moreover, a LVDS line is connected to a LVDS to TTL converter to handle a serial communication between the load and the external world. Only the receiver part of the line is shown in the figure below.
Circuit design-Page-1.png

Now assume that we want to get rid of the reset signal and that the power cannot be toggled at the origin. So the switch circuit must stay. To signal a reset we could imagine driving both the LVDS lines to a high impedance state. In such a case the switch circuit should detect this state and cut off the power. The power should be restored as soon as the LVDS lines go back to their normal common-mode voltage.
Untitled Diagram-Page-2.png

In other words, we would like to cut the power whenever the LVDS line is disconnected and restore the power when it is connected back.
Is that even possible? Could you point me in the correct direction for designing the switch circuit, please?
I have never seen something like this and googling "detect high impedance state" is not giving me anything very meaningful ...

Thank you
 

AlbertHall

Joined Jun 4, 2014
11,316
The LVDS lines should normally be opposite voltages. You could connect resistors to pull both lines high (or low) with sufficiently high values to not disturb the normal operation but when the lines are disconnected both lines will be the same level. You could detect that condition to signal that the lines are disconnected. You might need a filter or minimum pulse width detector on that signal as in normal operation both lines will be at the same voltage as they change state.
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
67
That is a good idea. I am going to try to implement it. By "filter" you mean an RC low pass filter to block pulses of length (and so frequency) less than a certain threshold?
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
67
@AlbertHall I have sketched a circuit according to your suggestion. The IC models and the values of resistors and capacitors are completely guesstimated and sloppy. This is just a proof-of-concept. I would be very happy if you could point out serious design flaws.

1622616256846.png

Labels explanation:
  1. Vsrc = 12V ~ 14V unregulated power supply
  2. RXD0_P, RXD0_N = LVDS signals (if they become high-impedance the comparator is triggered)
  3. BYWD-PWD-EN = to the enable pin of the main DCDC converter (but not directly). Basically if BYWD-PWD-EN becomes high, the power is switched off.
 

AlbertHall

Joined Jun 4, 2014
11,316
The comparator will not do the job. It is a very high gain amplifier and so any difference between the input voltages, however tiny, will drive the output to one of the supply rails.
What are the normal voltages of the LVDS lines?
 

andrewmm

Joined Feb 25, 2011
1,474
A good idea,
not certain how you could detect both lines "high impedance" without a comparator, that needs power

It may be difficult to get the sending end to make both lines "high", lvds has a small constrained voltage range,

How about two PSU's in the far end,
one to power the receiver thats always on, one to power the rest that is switched,
or can you have a reset that goes to the rest of the circuit, so all the circuit stays powered up, but in reset.
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
67
The comparator will not do the job. It is a very high gain amplifier and so any difference between the input voltages, however tiny, will drive the output to one of the supply rails.
What are the normal voltages of the LVDS lines?
You are absolutely right. I was completely misunderstanding the working principle of the comparator. I should probably use a couple of window comparators as the TLV170x family ANDed together.

By the way the LVDS lines should comply with the standard 1.2V common-mode voltage and 350mV voltage differential.
1622645932317.png
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
67
A good idea,
not certain how you could detect both lines "high impedance" without a comparator, that needs power

It may be difficult to get the sending end to make both lines "high", lvds has a small constrained voltage range,

How about two PSU's in the far end,
one to power the receiver thats always on, one to power the rest that is switched,
or can you have a reset that goes to the rest of the circuit, so all the circuit stays powered up, but in reset.
Thank you for the feedback.
The power to the comparator would come from the power line (separate from the LVDS lines).
I have no way to modify the power and signal source.
The whole point of this circuit is to eliminate the reset line.
 

AlbertHall

Joined Jun 4, 2014
11,316
You are absolutely right. I was completely misunderstanding the working principle of the comparator. I should probably use a couple of window comparators as the TLV170x family ANDed together.

By the way the LVDS lines should comply with the standard 1.2V common-mode voltage and 350mV voltage differential.
View attachment 240259
OK, so neither input should be below 0.5V. You could detect that a line was in that illegal zone using the comparator circuit you have but disconnect one input from the LVDS line and connect it to a potential divider across the supply with values arranged to make that input 0.5V. You can select whether you want a high or low output for loss of signal by choosing which comparator input is connected to the divider. This method should mean that no filter is needed as during normal operation neither line should bebelow 0.5V and so the comparator will never be tripped.
 

AlbertHall

Joined Jun 4, 2014
11,316
What about feeding the two LVDS signals to a NAND with a high-level input voltage set to less than 1V? Something like the Texas Instruments SN74AUC1G00 https://www.ti.com/product/SN74AUC1G00
The output of the NAND would be high only if both the LVDS lines are below one volt and be low during normal operation ...
Interesting. I think that would work but would need a low voltage supply for this chip.
 

andrewmm

Joined Feb 25, 2011
1,474
If the receiver is perminantly powered,

what speed is the LVDS ?

there are / were slower speed LVDS redrivers that have an input not connected output,
no use above 10 Mb/s

but a thought
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
67
The LVDS speed is quite low. Actually, there are 2 pairs of LVDS wires carrying the TX and RX signals of a UART connection at 115200 baud. The LVDS receiver is a SN65LVDS4 with VCC 1.8V and VDD 3.3V.
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
67
I simulated the circuit in LTSpice using the NAND approach and it is working as intended if the LVDS common-mode voltage is 1.2V.
1622712536712.png
 

andrewmm

Joined Feb 25, 2011
1,474
You need to be very careful,
LVDS outputs are current outputs, CML, not voltage
the voltage range of an output is there to specify what voltage range the current source / sinks of the LVDS output is compliment.
Thats why you need the 100 ohms across the + - of the pair to receive a voltage .

NAND gates,
depending what you select, can source / sink current that is noticable compared to the small current change that LVDS uses to indicate '1' or '0.

BTW,
at the transmitter,
how are you making the + and - output of a LVDS '1' at the same time,


At the speeds of a "RS232" link,
one of the "failsafe" circuits might be if use,

https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3662.html

https://www.ti.com/lit/pdf/slla082

https://www.ti.com/lit/an/snla051c/snla051c.pdf

You can safely put a second LVDS receiver across an input,
and use this output as the fail safe,
 

Thread Starter

LordOfThunder

Joined Jun 27, 2018
67
Sorry I have read again the thread and I only now realized that you were asking if the LVDS receiver IC was continuously powered or not. I misunderstood that question. The answer is: no, the LVDS receiver loses its power when the DCDC (LT3507) is powered down.
 
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