Xilinx ZCU102 has 10GigE SPF+ connector on the board. I am wondering about the signal on the PCB traces physically between FPGA and 10GigE SPF+ connector. There are only two differential pairs for 10GigE SPF+, one for Tx and one for Rx.
Is that digital signal running on the PCB traces which we sample at positive or negative edge of the clock ?
Is that analog signal on the signal traces on PCB between FPGA and 10GigE SPF+ connector ?

 

Xilinx ZCU102 has 10GigE SPF+ connector on the board. I am wondering about the signal on the PCB traces physically between FPGA and 10GigE SPF+ connector. There are only two differential pairs for 10GigE SPF+, one for Tx and one for Rx.
Is that digital signal running on the PCB traces which we sample at positive or negative edge of the clock ?
Is that analog signal on the signal traces on PCB between FPGA and 10GigE SPF+ connector ?

Oh dear,
Signals at giga bits per second are more rf analog than digital,
The signal is sent differential, 100 ohm differential,impedance, and needs to be very carefully routed, so the lines in the pair are length matched, and have very strict via requirements,
Yoyrvon the limit of what fr4vcan cope with,
Lookup the excellent pdf from xilinx on high-speed serial , its a great grounding.

 

@drjohsmith
Thanks for your reply. If the signal on the PCB traces is analog then I guess there would be equalizer and ADC on the receiver to sample the signal, right ?
In other words, we can not sample the signal on the PCB traces on positive edge and negative edge of the clock because the signal is analog on the traces.
Then on the transmitter side, there should be DAC on the FPGA side that that convert the digital data on to analog to transmit on the PCB traces.

Regarding PCB stack up. Is that a challenge to on FR4 based PCB. Can we still design and implement 10GigE on FR4 ? What other substrate with lower dielectric then FR4 can be used instead if not possible in FR4 ?

 

@drjohsmith
Thanks for your reply. If the signal on the PCB traces is analog then I guess there would be equalizer and ADC on the receiver to sample the signal, right ?
In other words, we can not sample the signal on the PCB traces on positive edge and negative edge of the clock because the signal is analog on the traces.
Then on the transmitter side, there should be DAC on the FPGA side that that convert the digital data on to analog to transmit on the PCB traces.

Regarding PCB stack up. Is that a challenge to on FR4 based PCB. Can we still design and implement 10GigE on FR4 ? What other substrate with lower dielectric then FR4 can be used instead if not possible in FR4 ?

If got 100 G running on FR4, its all possible,
no the signals are not analog, they are digital, but at these frequencies, one has to be aware of the analog principles of transmision , that at say 1 Mhz one does not,
If you read the free book I recomended, all this is explained in detail,
there is no clock and data lines, they are differential data, and the clock is encoded as part fo the 8:10 or what ever encoding scheme,
There are in deed equalisers, but that are on the transmitters not the receivers,
no point trying to equalise a duff signal, better to send a good signal
again all in the book I mentioned,
Id say , if your asking this , you need to get a qualified engineer involved in the project,
if you try and hope , withotu even readingand understanding the basic book referrenced, then you are going to fail,