Hi all,
I want to design a power supply for FPGA, where the core current can vary from few milliamps in sleep mode to about 16 Amps at maximum core usage. I have investigated a lot of switching regulators. Is there any pit fall that should be considered while designing the power supply which runs in both light load and very high load. Do the regulator in market can handle these cases easily or do I have to consider other special techniques??
Thanks for sharing your knowledge.
Nice weekends everyone!!
I want to design a power supply for FPGA, where the core current can vary from few milliamps in sleep mode to about 16 Amps at maximum core usage. I have investigated a lot of switching regulators. Is there any pit fall that should be considered while designing the power supply which runs in both light load and very high load. Do the regulator in market can handle these cases easily or do I have to consider other special techniques??
Thanks for sharing your knowledge.
Nice weekends everyone!!