What you need to do is forget the PL pin and use the 8 count to disable the relevant clock.
In other words, e.g. if you're counting up, when you reach 8, use it to disable the up input, but still allow count down. And vice versa!

can you explain it with proteus plz ?

 

can you explain it with proteus plz ?

Don't believe everything you see in a simulator.

 

Don't believe everything you see in a simulator.

so how to solve this issue i tried every thing nothing happend

 

Sarah and others have pointed out many errors in your design.

1) Switches must be debounced.
2) Pull down resistors must be 220Ω or lower for 7400 gates.
3) UP and DN inputs must be held high when idle.
4) Don't use PL. Gate the UP and DN inputs instead.
5) Reset switch is shorting the power supply.
6) You need a power-on reset circuit.
7) Pins 3, 4, 5, of 7447 should be tied high.
8) All circuits need 0.1μF decoupling capacitors and at least one 10μF across the power rails.

 

Sarah and others have pointed out many errors in your design.

1) Switches must be debounced.
2) Pull down resistors must be 220Ω or lower for 7400 gates.
3) UP and DN inputs must be held high when idle.
4) Don't use PL. Gate the UP and DN inputs instead.
5) Reset switch is shorting the power supply.
6) You need a power-on reset circuit.
7) Pins 3, 4, 5, of 7447 should be tied high.
8) All circuits need 0.1μF decoupling capacitors and at least one 10μF across the power rails.

I could 've done the holding on 8 can u help me in 0 bec it counts down to 9 which gate should i use to prevent counting down from 0 i tried or with all bits but didn't work

 

You need to detect the 0-state and inhibit COUNT DOWN.

R2 and R10 are now pull-ups. You don't need to go as low as 220Ω, 1k-4k7Ω will do. In any case, you still need to debounce the switches.

Your RESET switch still shorts out the power supply.

 

can you explain it with proteus plz ?

Sorry, I don't use Proteus or any simulators. The reason I know about the clocks both needing to be high is because I'm about to use the same I.C's in a project of my own.

 

Sorry, I don't use Proteus or any simulators. The reason I know about the clocks both needing to be high is because I'm about to use the same I.C's in a project of my own.

This is EXACTLY what I was trying to point out in my post but was hoping that you could discover more on your own. It’s an important skill to be able to understand a datasheet. And with logic circuits (such as counters) to be able to understand truth tables and timing diagrams. If you figure it out on your own, you will learn much more than if someone tells you what to do.

I don’t mean to pick on you, but your reply to my post merely parroted back what you had said before. And gave no indication that you had looked at the truth table to which I pointed you. Perhaps you did? I was trying to help.

 

I'd try this, if you have the I.C's.





The LS29 NOR gate detects the zero count and disables the B LS125, its output goes open circuit and is pulled high.
The same happens when an 8 is detected on the QD pin, LS125 A is disabled and its output goes high.
Since they are still high in the disabled state, the opposite count switch should still work.
You still need some of the other fixes that have been suggested.