I am trying to do my homework but have no idea where to start and how to solve it. Any hint or help will be appreciated.

This is the task:

Design a circuit which has two control inputs: RST and MOD and can generate at the output the following sequences of three-bit patterns in dependence on the RST and MOD input states:

After reaching the last pattern, the sequence repeats. The output state changes only at the active (rising) edge of the clock signal.
In your design you can use only standard logic gates (NOT, AND, OR, NAND, NOR, XOR, and XNOR) and flip-flops. Optimization of the combinational part of the circuit is mandatory and can be done either with the Karnaugh mapping technique or with Boolean algebra.
You need to describe the design process in detail, derive the logic circuit diagram and prove that it works according to the specification. The design process has to be conducted entirely by hand without the aid of any CAD tools such as a VHDL compiler, however, for the design verification CAD tools can be used.

 

You are being asked to design a time-state machine.

Check out this thread:
https://forum.allaboutcircuits.com/threads/up-down-decade-counter-using-d-flipflop.58572/

 

Okay, so now you need to show YOUR best attempt to solve YOUR homework. It doesn't have to be perfect, but it does have to exist. That gives us a starting point to help guide YOU along a path that will hopefully result in YOU solving the problem. Without that attempt, we have no clue as to what you understand, what you don't understand, how far you can get and where you run into problems.

Can you draw a state diagram for this machine?

Do you understand what this table is telling you and how to read it?