Decade 4-bit Synchronous Counter using D flop flop (Divide-by-2 Counter): Modify the following circuit so that it counts up from "0000" to "1000" and then resets. Use either AND, OR and Inverters or NAND gates.

Any help is appreciate.

 

That is not a synchronous counter. In a synchronous counter the same clock line would go to all four flip flops. What you have drawn is called a ripple counter and it takes a while for the counter to go from one stable state to another.

 

That is not a synchronous counter. In a synchronous counter the same clock line would go to all four flip flops. What you have drawn is called a ripple counter and it takes a while for the counter to go from one stable state to another.

Hello! Papabravo,

Thanks for info, could you please help me what should I do to modify the circuit to let it count up only from '0000' to '1000' instead of count from '0000' to '1111'?

Any hint is appreciate.

 

Your exercise is a classic one on designing a finite state machine.

Read the posts provided by tshuck:

http://forum.allaboutcircuits.com/threads/submission-another-look-at-synchronous-counters.82082/

On AAC tutorials:

http://www.allaboutcircuits.com/vol_4/chpt_11/5.html

I also partially covered this here:

http://forum.allaboutcircuits.com/threads/up-down-decade-counter-using-d-flipflop.58572/

 

In addition to the thread MrChips linked to, I also wrote a thread on modulus counters, which you may find useful as it includes an example of designing a decade counter using JK flip flops. The approach is the same, but your input forming logic will change.

 

Hello! Papabravo,

Thanks for info, could you please help me what should I do to modify the circuit to let it count up only from '0000' to '1000' instead of count from '0000' to '1111'?

Any hint is appreciate.

HINT: All your flip flops must be clocked by a common clock signal.
HINT: Design a decoder for the state '1000'
That's two hints before breakfast.