What are the outputs of a D flip flop?

And do you see anything unique about state 5? Especially as compared to states 1-4?

 

OMG yes, state 5 is the invers of state 1-4.
the outputs of a D flip flop are Q and Q invers.

so you need to take output Q for the first four states and Q invers for the fifth one somehow?

 

So we tried a different approach. A mod-5 counter that resets on 6. The output is 10101010101.
On the bottom side we connected additional logical circuitry so that when the counter is at 5 the circuit outputs a 0 anyway
This would make 1010010100... because the fifth one gets replaced by a zero every time.
However it still doesn't work, I really don't see the issue.
Is it just the simulating program that is wrong?

 

OMG yes, state 5 is the invers of state 1-4.
the outputs of a D flip flop are Q and Q invers.

so you need to take output Q for the first four states and Q invers for the fifth one somehow?

Yes, you’re close. But does that pattern match the desired output? What’s different or how can you easily get the desired pattern?

But there is something else in state 5 which you can use to select a different output for just that state...

 

Do you mean the first 1? Because you have 000, 001, 010, 011,100 which is the fifth state. Only the fifth state has a 1 on the first bit (which is the most right D flip flop on the picture). Is that what you mean?

 

Do you mean the first 1? Because you have 000, 001, 010, 011,100 which is the fifth state. Only the fifth state has a 1 on the first bit (which is the most right D flip flop on the picture). Is that what you mean?

Yes... re: the difference in the 5th state. Now, how can you use this to construct your pattern? You may need an additional component or two.

Take a look at individual bits output by your circuit. Remember my first hint.

Sometimes you have to recognize congruent patterns in solving a problem. Your earlier exercise with the K-maps illustrate this bit of knowledge.

 

I don't think there is a problem recognizing the fifth number. Currently we are detecting if the system is outputting 101. Detecting if the system is outputting 1(00) would be slightly more efficient but surely the outcome would be the same right?

The system shown above just isn't counting, the upper part isn't doing anything, which doesn't make sense to me. It seems to work on paper, and we've found other schematics online that show the same circuitry.
Thanks for being patient with us, but we've been searching for three days and we just can't seem to find it.

 

We have found the answer, thanks for helping though

 

To cement the concepts, consider this variant. You are given a 5-state machine that goes through the following sequence of states:

CBA
000
010
100
111
101

This is in a black box that you can't change, all you have are these three outputs. How can you get your 10100 sequence from there?

Note that I just picked those states at random, so I'm looking for an approach that will work for ANY sequence of five distinct 3-bit states.

 

By connecting to bit B, it goes 010100101001010...

 

You just got lucky.
How about this one:

CBA
000
100
101
111
010

 

By connecting to bit B, it goes 010100101001010...

So for any set of states you are just going to use bit B?

I'm looking for an approach that is guaranteed to work regardless of what states I choose and what order they end up in.

CBA
100
110
010
111
100

 

By taking Mrchips bits:
First three bits, put it on NOR gate so it outputs 1 if all are 0.
Second three bits, put second and third on invert and then combine to NAND, so outputs 0 of input is 100
Third, invert second bit and connect to AND gate so it outpits 1 if input is 101
Fourth, NAND
Fifth, invert first and third, connect to NAND

That would be my guess although it seems prettycumbersome, I wouldn't know any other way to make that work. Would love to know how though

 

By taking Mrchips bits:
First three bits, put it on NOR gate so it outputs 1 if all are 0.
Second three bits, put second and third on invert and then combine to NAND, so outputs 0 of input is 100
Third, invert second bit and connect to AND gate so it outpits 1 if input is 101
Fourth, NAND
Fifth, invert first and third, connect to NAND

That would be my guess although it seems prettycumbersome, I wouldn't know any other way to make that work. Would love to know how though

What you have described is a decoder circuit.
What we are asking is how does a 3-bit register go from one state to another, for example, from 100 to 110, or any two random states.

If we take the obvious binary sequence:

CBA
000
001
010
011
100

by a stroke of luck, output QA has the sequence you desire. Do you know how to connect three D-type flip-flops to generate such a sequence?

Do you know how to connect three D-type flip-flops to generate any random sequence such as the following:

CBA
000
100
101
111
010

 

Yeah, thats how we made our circuit
We used:
CBA
001
000
011
010
100

Where Qa is the desired output and the bits are not in order.

You make the current and next state tables, from there you know the state of D input and you can set up the logical circuits required for D.