I'm having trouble designing a circuit using multiple D flip flops. The task given to me is:
Design a sequential circuit with output Q. This output needs to output 10100 periodically. The frequency of said circuit doesn't matter.
Used D flip flop: IC: CD40175B quad D-type flip flop. The problem is we don't know how to change the output using only periodic input signals, like clock and D input.

Any help or insights would be greatly appreciated!

 

hello there
welcome to AAC. so I take it you have studied the addition and subtraction of binary , shift registers,full adders because you're going to need more than just a D flip flop.

 

You begin by drawing the truth-table of a D-type flip-flop.

 

You need to show your best attempt to work your homework. We will help you get past your immediate hurdle, but we won't work your homework for you.

What if the assignment had been to use multiple D FFs to implement a mod-5 counter. Could you have done that?

 

So for the truth table of the D flip flop and the half adder we have this.



A mod 5-counter could be implemented using 3 D flip flops because 2^3>5
when you have a signal of 110 (meaning 6) you use an invert on the 0 and connect these three outputs to an AND gate. This AND gate would toggle the clear making the counter restart.

We have made an 8 mod counter in figure 3, as seen in the transient analysis it is working fine.
In figure 4, we tried to make a 5 mod counter, this one however doesn't work. The system doesn't seem to be resetting.


Figure 3

Figure 4

We are thinking to produce a 01010 signal periodically for the task (which is the same as 10100 in the long term) which would mean we need 2^5bits or a mod-32 counter if I am correct.


Thanks for all the help

 

When you say that you need a Q output that produces the pattern 10100, I'm assuming that you mean that you have a single 1-but output that outputs 1...0...1...0...0...1...0...1...0...0...1...

If so, why would you need a mod-32 counter?

There are several way to solve the problem. I don't know what approach DeltaPrime has in mind. It's also hard to tell what type of solution your instructor is expecting because we don't know what specific course material is related to this assignment.

But if you can make a mod-5 counter, you have a circuit that cycles around five states. You have a pattern that consists of five values. Can you see a way to marry those two concepts together?

 

Having carefully studied the truth-table of a D-type flip-flop how can you produce an output sequence of 1-0-1-0-1-0 continuously?

 

The thing I don't get is, with a mod-5 counter you have 1 on Q1, 0 on Q2, 1 on Q3, 0 on Q4, 0 on Q5. But there needs to be only one output which goes 1, then 0, then 1, then 0, then 0, then 1...

Also by using a counter, wouldn't you have to wait until the system gets to 10100 every time before something happens? Because all the other states are don't cares?

 

The way to get 1-0-1-0-1-0 in a D-type flip-flop is to connect your Q invert to D input I think, this will flip the output each time your clock cycles.

 

The thing I don't get is, with a mod-5 counter you have 1 on Q1, 0 on Q2, 1 on Q3, 0 on Q4, 0 on Q5. But there needs to be only one output which goes 1, then 0, then 1, then 0, then 0, then 1...

Also by using a counter, wouldn't you have to wait until the system gets to 10100 every time before something happens? Because all the other states are don't cares?

You have:
1
0
1
0
0

Ignore the pattern for now.
How many unique states are these?

 

2 states? 0 and 1

 

The thing I don't get is, with a mod-5 counter you have 1 on Q1, 0 on Q2, 1 on Q3, 0 on Q4, 0 on Q5. But there needs to be only one output which goes 1, then 0, then 1, then 0, then 0, then 1...

Also by using a counter, wouldn't you have to wait until the system gets to 10100 every time before something happens? Because all the other states are don't cares?

As you said earlier, with a mod-5 counter you have five states and need three flip flops to implement it. Your states will be 5 of the 8 possible combinations. You can design the counter to be any five of those states in any order that you want. But let's just pick them in normal binary order:

# S2 S1 S0
0  0  0  0
1  0  0  1
2  0  1  0
3  0  1  1
4  1  0  0

If the first of those states, you want your output to be a 1. In the second, you want it to be a 0. And so on. Can you make a truth table for what you want the output to be in each of those states? Can you then design a circuit that implements that truth table?

 

2 states? 0 and 1

You have:
1
0
1
0
0

The first 1 is unique from the second 1. That makes 2 states
The first 0 is unique from the second 0. The third 0 is unique from the first and second 0. That makes 3 states.
In all, there are 5 unique states.

Hence you need a finite state machine with 5 states.

 

so we used a 3-bit irregular count sequence that has 5 unique states to implement the system. Here Q0 is the output we want.
From the transition tables, the present and next state tables we can make the karnaugh maps and get each input of the D flip flops.



This is the circuit we end up with, but it still doesn't work. Which makes sense because currently no D input will be high so the system won't start. What would need to be changed and is this the right way to go?

Thanks again for the help.

 

I'm sorry, I don't know if you can see the Images in full resolution.
I can on my screen but I don't know if its clear on the other side.

 

A question and a hint...

What is the “twist” in this problem? How can you use what you’ve done so far to resolve this “twist”?

You want 10100... What if you can get 01011?

 

If we can get 01011 all we would have to do is invert it to get the desired output.
Why would we be able to make 01011 if 10100 doesn't work?

We have made the table for 01011, but the answer is the same as 10100 which doesn't make sense at all. That means we would have to get 10100 and 01011 at the same time.

I guess we are doing something wrong when setting up our tables with Q2 and Q1.
We are trying to make a 5-mod counter which counts these 5 unique states and Q0 would be the output.
Clearly we are doing something wrong, we don't know what the twist is.

 

so we used a 3-bit irregular count sequence that has 5 unique states to implement the system. Here Q0 is the output we want.
From the transition tables, the present and next state tables we can make the karnaugh maps and get each input of the D flip flops.



This is the circuit we end up with, but it still doesn't work. Which makes sense because currently no D input will be high so the system won't start. What would need to be changed and is this the right way to go?

Thanks again for the help.

Look at your K-maps. In each one you have blindly circled the entire table and declared it to be equal to one of the state variables. Does that make sense? You can only circle groups of states that are either 1 or X. You can't include ANY 0s in your groups.

 

We have made the table for 01011, but the answer is the same as 10100 which doesn't make sense at all

If we can get 01011 all we would have to do is invert it to get the desired output.

Why would we be able to make 01011 if 10100 doesn't work?

Your second comment answers the first question. It does make sense because one pattern is just the inverse of the other. What feature of the D flip flop makes this simple?

Your assumption that you can’t make 10100 can’t work is incorrect. It can work; you just haven’t discovered how.

I mentioned 01011 because perhaps you can see a pattern there when reviewing the datasheet. Especially in states 1-4.

 

Thanks for telling, we corrected the K-maps. Yet again no output. The problem is the AND-gates will never open because when starting the circuit no 2 connections to the AND gates will be high.




Making a 1010101.... flip flop would be easy, by connecting the Q invers to the D input. we just need 2 zero's between the second and third 1, between the fourth and fifth,...