From what I can tell, this circuit drives the PMOS(enhancement) to create a current source. The VS2-supply will be a 20V @ 2A(max) output of a power supply, while the VS1-supply would be the output of a DAC with outputs for currents that we want- in this case 50mA intervals of 78.125mV steps. My current issue is with simulating this circuit. During various steps (no apparent rhyme or reason) the maximum current will be seen on the load even though the "set current" will be much lower. I cannot figure out why and would appreciate any help on what this circuit is and how to modify it correctly.

Also of note VS3=VS2, however I split it for sake of visual cleanliness.

 

Have you check if your circuit is not showing the signs of oscillations?

 

Have you check if your circuit is not showing the signs of oscillations?

There are no oscillations on the load. I have not looked elsewhere

 

Ok, I did some calculations and I found that your circuit transconductance should be around gm = 1/0.25Ω * 5.1kΩ/30kΩ = 0.68S hencs for Vin = 78.125mV the expected output current is IL = 0.68S*78.125mV = 53.125mA.

And the LTspice is showing IL = 53.296mA but also I see the signs of oscillations.
Also, can you specify your problem more clearly? And you could try to use N-channel MOSFET instead of a P-channel (of course you need to swap the op-amp inputs).

 

Ok, I did some calculations and I found that your circuit transconductance should be around gm = 1/0.25Ω * 5.1kΩ/30kΩ = 0.68S hencs for Vin = 78.125mV the expected output current is IL = 0.68S*78.125mV = 53.125mA.

And the LTspice is showing IL = 53.296mA but also I see the signs of oscillations.
Also, can you specify your problem more clearly? And you could try to use N-channel MOSFET instead of a P-channel (of course you need to swap the op-amp inputs).

So to clarify, my resistor dividers could be changed in such a way that would give me the desired output?

The problem is at say Vin= 2.1875V , IL= 1.576A when it my DAC mapping is calling for 1.4A. The next two steps, 2.26563V (1.45A) and 2.34375V (1.5A) are also around 1.578A.

But I think you may have found the solution.

 

Are you talking about the simulations result (DC or transient analysis) or real-world measurements?
Also, try to add a 1nF capacitor between U1 output and U1 inverting input.

 

Are you talking about the simulations result (DC or transient analysis) or real-world measurements?
Also, try to add a 1nF capacitor between U1 output and U1 inverting input.

Talking about simulation results- Transient analysis.

The real-world circuit exists, however, I do not want to make changes to it until I am satisfied with theoretical results.

 

A quick calculation i get about 1.5v input voltage per output ampere.

But yes a PNP type transistor in this kind of application (as well as the P MOSFET) could easily and most likely will oscillate. It is very hard to compensate this setup for EVERY type of load.
If you only intend to use a resistive load with set value capacitor then it may be possible.

The simplest way to do this is with an NPN transistor probably one small and one larger to get enough gain.
The problem with the PNP or P MOSFET is that it adds gain inside the forward gain path and that can cause oscillations because the op amp is compensated for a particular max internal gain. Once you add more gain to the op amp it becomes unstable for certain loads. It's hard to compensate for all load types because the load changes the loop response.
Using an NPN adds a gain of 1 or slightly less than 1 so the op amp does not have this problem. You may still need some compensation for some load types however. Pure resistive should be ok though.

 

Unfortunately I am not the original designer of this circuit and have no idea what it exactly is or how it was designed in the first place.

The load will not be static or purely resistive - even though I modeled it as such for the question. The real load is a coil with a Rser as shown above. This is driven by an H-bridge for +/- current flow through the coil.

 

View attachment 195423

From what I can tell, this circuit drives the PMOS(enhancement) to create a current source. The VS2-supply will be a 20V @ 2A(max) output of a power supply, while the VS1-supply would be the output of a DAC with outputs for currents that we want- in this case 50mA intervals of 78.125mV steps. My current issue is with simulating this circuit. During various steps (no apparent rhyme or reason) the maximum current will be seen on the load even though the "set current" will be much lower. I cannot figure out why and would appreciate any help on what this circuit is and how to modify it correctly.

Also of note VS3=VS2, however I split it for sake of visual cleanliness.

What is the voltage out of VS1?

 

What is the voltage out of VS1?

VS1 can be any of the following (with expected output currents):

Set to Current	Voltage Out
0​	0​
0.05​	0.07813​
0.1​	0.15625​
0.15​	0.23438​
0.2​	0.3125​
0.25​	0.39063​
0.3​	0.46875​
0.35​	0.54688​
0.4​	0.625​
0.45​	0.70313​
0.5​	0.78125​
0.55​	0.85938​
0.6​	0.9375​
0.65​	1.01563​
0.7​	1.09375​
0.75​	1.17188​
0.8​	1.25​
0.85​	1.32813​
0.9​	1.40625​
0.95​	1.48438​
1​	1.5625​
1.05​	1.64063​
1.1​	1.71875​
1.15​	1.79688​
1.2​	1.875​
1.25​	1.95313​
1.3​	2.03125​
1.35​	2.10938​
1.4​	2.1875​
1.45​	2.26563​
1.5​	2.34375​