I am struggling to understand the difference between making a binary upcounter and making an upcounter that increases by 5. How is one supposed to go about that?

 

Hello Michael Daugherty

The difference between making a Binary Up-Counter and make an Up-Counter that increases by 5 is that:
The binary Up-Counter will count: 0, 1, 2, 3, 4, 5, Etc.
And an Up-Counter that increases by 5 will count: 0, 5. 10, 15, 20, Etc.
Note: for convenience numbers are represented in decimal, not in binary.


How to do it ?.
Well. the first counter should count in increments of 5.
Use the least significant BIT of the first counter.
In the binary to BCD decoder you must achieve That when the counter is at 0 light a 0 in the display and when in 1 light a 5.


That same BIT, of first counter, you can used to have +1 in the tens counter.

You will notice, that this is misleading because the first counter will count 0, 1, 2, 3, 4, 5, Etc.
You can, in this case, use a simple Flip-Flip as counter for units.

I hope I've helped.

 

That did help somewhat, thanks! What I'm still confused on is how the counter stores this in memory without using a display? Does that make any sense?

 

I'd just assign the LSB a value of '5'. Stripping that from the rest of the bits leaves n*10, where n is the binary value of the remaining bits.

Pretty easy.

 

Reading between the lines, I think the desired result is a counter with binary outputs that increments by 5h with each clock pulse. Conceptually, a clocked full adder with 5 as one addend and the output fed back as the other addend.

ak

 

Or, for a completely different option, you can have a switch trigger a monostable 555 timer, the output of that timer pulls the reset pin on an astable 555 circuit long enough to allow the astable 555 to cycle 5 times.

The astable 555 should be capacitively coupled so the monostable is independent of button press time.

 

Hello Michael Daugherty

Memory. . . What memory ??.
You mean the feature of 'memory' that the Flip-Flops has with whom Counters are made. ??

Well, let making a synchronous counter with JK Flip-Flops.
But we must establish certain conventions:
A Q outputs give them a value, as is usually done with counters:
The least significant Q will call Q1, Q2 the next, the third Q4 and Q8 the most significant.

So when Q1 and Q4 have a high logic level will have our 5(Dec). 0101(Bin).
And when all Q's are low logic level will have our 0(Dec). 0000(Bin).

J and K inputs have the value of its Q.
For example: J1 and K1 be in the Flip-Flop whose Q is Q1. and so on.

Now you can analyze the circuit contained in the PDF document I am enclosing you.
You can see that there are many devices in the design left over.
If you have a simulator for electronic circuit design You can develop that I am enclosing which was developed with the ISIS Proteus simulator. (Contained in the ZIP file).
You can take as an example the design contained in the PDF document attached to develop it in other simulator.

Mod edit: reduced file size on .PDF

 

Hello there,

There are probably a lot of ways of doing this, depending on what the other requirements are such as if you dont need it to be synchronous, and if you are allowed to use adders. For very large counts adders may not be allowed for example.

So if a ripple carry binary counter is acceptable and this has to be pure binary (not BCD) then you can simply create the first stage of the counter with flip flops where you can either clock the first FF or the third FF. If you clock the first FF you increase the total count by 1, and if you clock the third FF you increase the total count by 4, so obviously if you first clock the first FF and then quickly clock the third FF the count would have increased by 5, and that's in pure binary. The two FF's must be clocked sequentially however not both at the same time. This is similar to a 'burst' method where you clock with a burst of 5 clock pulses.

That's probably the simplest method, but if you are not allowed to advance the count in two steps (there will be an intermediate state where the count is not exactly correct) then you either need to add storage or do it in a different manner, which brings us to another solution...

If you create a counter with a variable first stage, you can accomplish the task with just one clock pulse. The first stage would be created from THREE down counters, not up counters. One of the three would be selected through gating to be the actual counter being used.

To start, we could label the three counters as A, B, and C. We need to pre-load these three counters with 0000, 0101, and 1010 to start, so they also need to be loadable down counters.
A secondary counter counts from 0 to 2, then back to 0, and is used to 'select' one out of the three first stage counters.

Thus when the secondary counter equals 0 we get 0000 on the output of the first stage, then when the secondary counter equals 1 we get 0101 on the output, then when it goes to 2 we get 1010 on the output, which is the count 0, 5, 10 which is counting by 5's.

Next, when the secondary counter flips back to 0, we DECREMENT all three counters. Note that when counter A is decremented by 1 it becomes 1111. So the next output is 1111. Note also that when the counter B is decremented by 1 it becomes 0100,so the next output is 0100 but because 0100 is less than 1111 we also increment the next FF in the stage, which would be the next bit of the full counter. So the count would go from 0000 1111 to 0001 0100 which is "20" decimal.
This also requires a four bit latch and comparator to detect when the output of the first stage goes from a higher count to a lower count, at which time the next FF bit is clocked up by 1.

If you follow this design method you can create a counter of any size by just adding more flip flops, no need for adders or sequential clocking.

If you have a very very small counter with a low bit count, you can also use a PROM to do the conversion from a binary count by 1 counter to an output that appears to increase by 5's.
You could however also use a PROM to pre-program the first stage activity with an extra output for the 'carry' for the next FF bit stage. That would be a very simple design.

As i said, there are many ways to do this and it is interesting to look at different ways. The variable first stage method works because after a certain count the pattern repeats.

 

A Q outputs give them a value, as is usually done with counters:
The least significant Q will call Q1, Q2 the next, the third Q4 and Q8 the most significant.
So when Q1 and Q4 have a high logic level will have our 5(Dec). 0101(Bin).

In your nomenclature, Q1 and Q4 equal 9. Q1 and Q3 equal 5.

Also, most counters and other multi-bit components such as latches and transceivers start the output bit sequence with Q0, not Q1. See data sheets for the 7416x, 7419x, 7437x.

ak

 

Hello Analog Kid
.
Yes, certainly different manufacturers of these devices named to the Q's as 0, 1, 2, 3.
But Hitachi's named as A, B, C, D.
.
In the different simulators for electronic circuits also named differently to these Q's.
For example LiveWire simulator name as 1, 2, 4, 8.
The ISIS Proteus simulator gives them the name of 0, 1, 2, 3. Except for the 40192 and 40192 in which case gives the name of A, B, C, D.
If I'm not mistaken, the Multisim simulator gives the name to Q's such as A, B, C, D.
.
Those names, that are given to the different inputs and/or outputs, for Me, are conventional.
I think the important thing is to know that Q changes every pulse, each two pulses, every four pulses, every eight pulses.
.
But let's see what is meant by 0, 1, 2, 3.
2 to the power of 0 = 1.
2 to the power of 1 = 2.
2 to the power of 2 = 4.
2 to the power of 3 = 8.
.
So to Me, it's easier, for example, if I want to stop a counter at 10, simply select Q8 and Q2 because the sum of it's values give mi 10. And so for any number from 0 to 15. In this case.