Hi folks,

This is my first experience trying to route CPU to external memory IC's with more than 1 memory chip. Even worse, there is 2 SDRAM + 2 Flash IC's.

6ML


Well, the question is fundamental.. Will this routing actually work? I'm feeling not sure because some traces are about 4-5" long with not really much space between them, which result in impendance, resistance, capacitance, bla bla...

Any suggestions or hints?

Thanks!

 

Frequency and part numbers please...

 

Frequency and part numbers please...

CPU is ARM9 @ 180 MHz
SDRAM : 2 x Micron MT48LC16M16A2 (256Mbit, 7.5ns/CL=2 -> PC133)
FLASH : 2 x Atmel AT49BV642D (64Mbit, 70ns)

In fact, the access times may be configured at CPU.

 

I'm taking wild guesses at trace width, separation, and thickness. I'm therefore guessing half a microhenry per meter, or 76 ohms between worst case traces.

For a more accurate answer, go here.

 

Btw, layer stack-up for PCB:

1 - TOP
2 - SIGNAL
3 - PWR
4 - GND
5 - SIGNAL
6 - BOTTOM

After resolving few questions, I think this board will have in result 8 layers for 2 additional ground planes because of layer to layer impendance on top and bottom.

1 - TOP
2 - GND
3 - SIGNAL
4 - GND
5 - PWR
6 - SIGNAL
7 - GND
8 - BOTTOM

I was said that if traces are less for 6" (delay of 1ns) this will work.

What do you think, people?

 

If you are going to end up with 8 layers anyway, I think you should revise the layout. Move the chips in-line and closer together, avoid changing layers on the bus and go with vertical and horizontal layers. Try to make the tracks somewhat similar in length, it's a good idea to do this even with PC133.

What layout package are you using?

You could always loosen the timing if they didn't work

 

Well, the situation is that there is not much time left for this project, that's why I don't really want to revise layout and reroute this again

Btw, the difference between shortest(1044mil) and longest(5198mil) track is about 4154mil (4.154"). Impendance variation is 79.93-55.03=24.09Ohm.

You could always loosen the timing if they didn't work.

Rising edge flight time is 1.48ns and falling is 4.4ns. Signal integrity says this will this work without loosing access time?

What layout package are you using?

Altium Designer 6. Not seen better at this moment.

 

If you have not much time left, then you could go ahead with the current layout. As I said previously, if things do indeed go wrong, you have an option to loosen the timing.

The signal integrity on Altium is pretty good, you could rely on it most of the time.

How do you cope with the un-intuitive interface? It totally put me off that context menus, or double clicks resulted in totally different things than what's normally expected. And the pain to change components properties or values. But that's just me

 

If you have not much time left, then you could go ahead with the current layout. As I said previously, if things do indeed go wrong, you have an option to loosen the timing.

The signal integrity on Altium is pretty good, you could rely on it most of the time.

Thanks very much! This is what I wanted to hear. After I'll get assemblied pcb, I'll let know about the results.

How do you cope with the un-intuitive interface? It totally put me off that context menus, or double clicks resulted in totally different things than what's normally expected. And the pain to change components properties or values. But that's just me

Well, I had to In time You'll get quite familiar and fast enough, believe me. For example, changing properties/values for a lot of components at the same time is possible within Tools>Parameter Manager>Parts. Just highlight few rows, right click, edit, ..., accept changes. PCB filters is also awesome for changing, for example, all the ground vias hole diameter.
Indeed, the interface is really complicated and it is easy to run deep into forest. But You know, there is also a lot of things hidden there