CPLD for project
- Thread starter shaklack
- Start date
Analog Ground
- Joined Apr 24, 2019
- 460
The rise and fall times for a CPLD output is a complicated parameter. Data sheets provide setup and hold times and propagation delays but rise and fall times for general purpose outputs, not so much. A lot depends on what is loading the pin. In general, IBIS or Spice modeling is done to determine the rise and fall times for specific conditions. Or, actual measurements which are difficult without the right kind of oscilloscope and probe. In my experience, 2 nanoseconds rise or fall time is a reasonable number for a device such as a MAX10 from Intel. Again, what is the load? What rise and fall times do you need? Some of the specialized outputs are very fast with subnanosecond timing but these are output types like LVDS.
Edit: Going much faster then a couple of nanoseconds starts to cause problems such as ground bounce. So, general purpose outputs will, in general, not go much faster. These problems are so common that many CPLDs have the option to slow down the output slew rate. For example, the MAX10 device I mentioned earlier has fast, medium and slow options for general purpose outputs. Slew rate control saved me once when I had a large number of outputs switching at the same time. I had to use the slow option.
Edit: Going much faster then a couple of nanoseconds starts to cause problems such as ground bounce. So, general purpose outputs will, in general, not go much faster. These problems are so common that many CPLDs have the option to slow down the output slew rate. For example, the MAX10 device I mentioned earlier has fast, medium and slow options for general purpose outputs. Slew rate control saved me once when I had a large number of outputs switching at the same time. I had to use the slow option.
Last edited:
ronsimpson
- Joined Oct 7, 2019
- 3,047
SN74AUC2G06DCKR
There is a series of small logic that is fast. Most of the parts are in 6 or 8 pin packages. So only simple logic.
SN74AUC2G08DCUR
74LVC1G04W5-7
If we could see clearly what you want to do.....
There is a series of small logic that is fast. Most of the parts are in 6 or 8 pin packages. So only simple logic.
SN74AUC2G08DCUR
74LVC1G04W5-7
If we could see clearly what you want to do.....
Deleted member 115935
- Joined Dec 31, 1969
- 0
A few things.
CPLD's are getting rare, and you will need a programmer to get the code into them,
great thigns, I use them all the time, but Im set up to use FPGAs and CPLD's.
Speed, you are not going to find a CPLD that runs such that you can make a 1 ns pulse.
At sub ns, your into the world of making glitches, which are very difficult to see / test design , especially in something reliable and low cost.
If you really want 1ns pulses, then you are into the world of ECL.
I use these chips,
https://www.mouser.co.uk/datasheet/2/308/MC100EP016A-D-1811047.pdf
as part of a ECL "edge" detector, driven by a slower FPGA.
the FPGA makes a rising edge, and the ECL edge detector makes a 1 ns pulse out of the rising edge.
BUT, please dont ask can I have a 12 volt output as some on did the other week...
CPLD's are getting rare, and you will need a programmer to get the code into them,
great thigns, I use them all the time, but Im set up to use FPGAs and CPLD's.
Speed, you are not going to find a CPLD that runs such that you can make a 1 ns pulse.
At sub ns, your into the world of making glitches, which are very difficult to see / test design , especially in something reliable and low cost.
If you really want 1ns pulses, then you are into the world of ECL.
I use these chips,
https://www.mouser.co.uk/datasheet/2/308/MC100EP016A-D-1811047.pdf
as part of a ECL "edge" detector, driven by a slower FPGA.
the FPGA makes a rising edge, and the ECL edge detector makes a 1 ns pulse out of the rising edge.
BUT, please dont ask can I have a 12 volt output as some on did the other week...
