Hello

I need help with counter scheme.
Counter count like that: 0 -> 1 -> 2 -> 3 -> 4 -> 1 -> 2 -> 4 -> 8 -> 4 -> 3 -> 2 -> 1 -> 0
Already I have this part: 0 -> 1 -> 2 -> 3 -> 4 and it's working, but I have no idea how to get next states....
Can someone help me ?

 

How many states are in your sequence?

 

Welcome to AAC!

I need help with counter scheme.
Counter count like that: 0 -> 1 -> 2 -> 3 -> 4 -> 1 -> 2 -> 4 -> 8 -> 4 -> 3 -> 2 -> 1 -> 0

Are you required to use an asynchronous (ripple) counter?

 

Sometimes the "4" transitions to a "1", other times the "4" transitions to an "8", and still other times the "4" transitions to a "3". How will the counter keep track of what to do with the "4"?

 

View attachment 207741
Sometimes the "4" transitions to a "1", other times the "4" transitions to an "8", and still other times the "4" transitions to a "3". How will the counter keep track of what to do with the "4"?

The same is true with most of the other outputs. That's why it's important to recognize the number of states in the sequence of outputs, not the number of different outputs.

 

Thanks for all of your replies.
I did some research and I think it should be synchronous counter.
This table show how it should work.

Outputs: S0 to S4

 

So if you are in State [0][0][1][0], what state do you go to next?

Remember, a counter ONLY knows what state it is currently in. It has no other record of it's history. So it has to be able to decide what state to go to next based ONLY on what state it is currently in.

Leaving that aside, look at your table closely. Does it really represent either the sequence you are supposed to do (what what contained in your original post) or the encoding of each value that you intended?

 

So table represents sequences.
I have to make synchronus counter from 4 j-k flip-flops and some logic gates. This counter has 3 states of work. And I don't know how to set circuit properly to this table;/

 

I have to make synchronus counter from 4 j-k flip-flops and some logic gates. This counter has 3 states of work. And I don't know how to set circuit properly to this table

Are you supposed to display the sequence on discrete LEDs? Or on a seven segment display?

Things might be clearer for us if you posted the entire text of the problem.

 

Outputs may be displayed by binary probe

 

Outputs may be displayed by binary probe

Full text for the problem would be helpful.

 

So table represents sequences.
I have to make synchronus counter from 4 j-k flip-flops and some logic gates. This counter has 3 states of work. And I don't know how to set circuit properly to this table;/

How do you arrive at "3 states of work"? What are those states?

If you have to make a synchronous counter, then why does your original post show an asynchronous counter?

Please post the entire text of the actual problem so that we know what you are trying to achieve.

 

Your problem is difficult if you do not know the formal techniques involved in creating "state machines" or "custom counters". Do you know the basics of the following logic design topics?
1. Flip Flop excitation tables. In particular, a JKFF or DFF.
2. Showing "present state" and "next state" information for a state machine in a truth table. (See Post #2)
3. Using Karnaugh maps derived from the truth table and the FF excitation tables to perform logic minimization.
4. Using the results of the Karnaugh maps to produce a circuit using logic gates.
Given your problem, I would think these would be topics taught in your class. It is possible to design a solution through trial and error and inspection but knowing the logic topics in my list is much, much better and will get you a better grade.

 

This counter has 3 states of work.

It almost appears as though there are 3 different counters, and you are switching between them.

 

It almost appears as though there are 3 different counters, and you are switching between them.
View attachment 207771

The OP mentions using four flip flops. If there is a limit of four, it really limits the design options. Maybe only one? IMHO, it would have to be a classic state machine designed along the lines I list in Post #13.

 

The OP mentions using four flip flops. If there is a limit of four, it really limits the design options. Maybe only one?

Only one what? Design option using four flip flops? If I'm counting right, I get about 3.5 trillion design options.

 

The OP mentions using four flip flops. If there is a limit of four, it really limits the design options.

Why would only being able to use 4 flip flops be a hindrance?

 

Only one what? Design option using four flip flops? If I'm counting right, I get about 3.5 trillion design options.

Not the detailed design, the general architecture. For example, the outputs could not directly be the flip-flop outputs. The FF outputs would have to be decoded to produce the count outputs. If more than four FFs, the outputs could be directly from the FFs. That kind of thing. Or, for example, the approach suggested in Post #14 would not work. That kind of thing. I hope this clarifies my assertion. Any more detail and I am giving away the answer to the OP.

 

Why would only being able to use 4 flip flops be a hindrance?

Not a hindrance. Possibly a limit set by the homework problem. Restricting the number of FFs can make a big impact on the design. I am glad to see someone reads my posts!

 

Restricting the number of FFs can make a big impact on the design.

I'm still waiting for the OP to post the entire text of the problem. I was skeptical of the problem description from my first post and have asked for the complete text of the problem - twice.