Hi there
I want to design a logic circuit that countdown from 6 downto 0.

so that is 110->101->100->011->010->001->000->110

This is my circuit (using CEDAR), the led display number 6



but something weird happen, when I give the circuit another pulse, the number countdown to 2!!

When I simulated step by step, I found out a huge problem. Let call the left D-FF is the LSB and the right D-FF is the MSB. When it counts from 6 to 5 (110 downto 101), the signal Q from the left D-FF (LSB) now is 1 and it go to the NAND gates, whose input now is 1-1-1, and it reset the entire loop to 6. (110). Because the signal Q of the middle D-FF went from 0 to 1, the right D-FF is counted from 1 to 0. As the result, the set of Q signals now is 010.

 

oh sorry, I forgot the question. Is this software problem or circuit problem? (because I design this circuit follow the instruction on textbook)

 

oh sorry, I forgot the question. Is this software problem or circuit problem? (because I design this circuit follow the instruction on textbook)

Dont think so. I simulated with Proteus and I couldn't even start the circuit.

The problem is that when the 3 outputs is '000' when switched on. You NOR gate would force the outputs to '110'. The condition in the S and R is permanent, so the 3 F/F are locked in that condition.

You need to send a positive pulse from the NOR gate instead of a permanent state. A 100nF with a 10K resistor would do the trick.

Allen

 

Welcome to AAC!

I want to design a logic circuit that countdown from 6 downto 0.

Is this homework?

 

Welcome to AAC!

Is this homework?

Yes, it is small homework. I have to design the asynchronous countdown from 6 downto 0 with D-FF

 

Dont think so. I simulated with Proteus and I couldn't even start the circuit.

The problem is that when the 3 outputs is '000' when switched on. You NOR gate would force the outputs to '110'. The condition in the S and R is permanent, so the 3 F/F are locked in that condition.

You need to send a positive pulse from the NOR gate instead of a permanent state. A 100nF with a 10K resistor would do the trick.

Allen

I quite don't understand "3 outputs is '000' when switched on. You NOR gate would force the outputs to '110'." Because that is a NAND gate and it only send positive output when 3 of them are '111'

 

Yes, you're right. I changed your NAND gate to NOR as my D/FF was active high on Set and clear.
I am using 4013 cmos DFF while you're using 7474 DFF.

So you're detect '111' and the AND gate set the outputs to '110' then what happens?

Allen

 

When I simulated step by step, I found out a huge problem. Let call the left D-FF is the LSB and the right D-FF is the MSB. When it counts from 6 to 5 (110 downto 101), the signal Q from the left D-FF (LSB) now is 1 and it go to the NAND gates, whose input now is 1-1-1, and it reset the entire loop to 6. (110). Because the signal Q of the middle D-FF went from 0 to 1, the right D-FF is counted from 1 to 0. As the result, the set of Q signals now is 010.

So that's why you have to use 3-input-NOR to detect '000' not '111' for the FF to reset back to '110'. Try it and it should work.

Allen

 

Yes, it is small homework. I have to design the asynchronous countdown from 6 downto 0 with D-FF

Are you still working on this problem?

I had installed this simulator on my computer years ago. Now I remember why I decided not to use it...

 

https://www.google.com/search?q=dow.....69i57j0l5.6688j0j8&sourceid=chrome&ie=UTF-8