Hi All,
I have the following VHDL code that I would like to convert to verilog:
signal dtemp : unsigned(17 downto 0);
signal din_buf : signed(17 downto 0);
signal dtemp1 : integer;
constant offset : unsigned(17 downto 0) := "000100000000000000";
din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&din;
dtemp <= dtemp + unsigned(din_buf) + offset;
dtemp1 <= to_integer(dtemp(17 downto 8));
My attempt is:
reg [17:0] dtemp;
reg signed [17:0] din_buf;
integer dtemp1;
parameter [17:0] offset = 18'b 000100000000000000;
din_buf <= {din[11], din[11], din[11], din[11], din[11], din[11], din};
dtemp <= dtemp + $unsigned(din_buf) + offset;
dtemp1 <= $signed(dtemp[17:8]);
My biggest problem is the VHDL "to_integer" designator, the closest I have come up with in Verilog is "$signed"
Any suggestions most welcome.
Cheers
I have the following VHDL code that I would like to convert to verilog:
signal dtemp : unsigned(17 downto 0);
signal din_buf : signed(17 downto 0);
signal dtemp1 : integer;
constant offset : unsigned(17 downto 0) := "000100000000000000";
din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&din;
dtemp <= dtemp + unsigned(din_buf) + offset;
dtemp1 <= to_integer(dtemp(17 downto 8));
My attempt is:
reg [17:0] dtemp;
reg signed [17:0] din_buf;
integer dtemp1;
parameter [17:0] offset = 18'b 000100000000000000;
din_buf <= {din[11], din[11], din[11], din[11], din[11], din[11], din};
dtemp <= dtemp + $unsigned(din_buf) + offset;
dtemp1 <= $signed(dtemp[17:8]);
My biggest problem is the VHDL "to_integer" designator, the closest I have come up with in Verilog is "$signed"
Any suggestions most welcome.
Cheers