Hi All,

I have the following VHDL code that I would like to convert to verilog:

signal dtemp : unsigned(17 downto 0);
signal din_buf : signed(17 downto 0);
signal dtemp1 : integer;
constant offset : unsigned(17 downto 0) := "000100000000000000";

din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&din;
dtemp <= dtemp + unsigned(din_buf) + offset;
dtemp1 <= to_integer(dtemp(17 downto 8));

My attempt is:

reg [17:0] dtemp;
reg signed [17:0] din_buf;
integer dtemp1;
parameter [17:0] offset = 18'b 000100000000000000;

din_buf <= {din[11], din[11], din[11], din[11], din[11], din[11], din};
dtemp <= dtemp + $unsigned(din_buf) + offset;
dtemp1 <= $signed(dtemp[17:8]);

My biggest problem is the VHDL "to_integer" designator, the closest I have come up with in Verilog is "$signed"

Any suggestions most welcome.

Cheers

 

Since most synthesis tools that I have worked with can convert either VHDL or Verilog to RTL, why would you want to risk 'breaking' hardware by trying to convert it from one HDL to another? I am not stating you don't have a valid reason for doing so, which is why I am posing the question before trying to answer the primary question.

 

Hi All,

I have the following VHDL code that I would like to convert to verilog:

signal dtemp : unsigned(17 downto 0);
signal din_buf : signed(17 downto 0);
signal dtemp1 : integer;
constant offset : unsigned(17 downto 0) := "000100000000000000";

din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&din;
dtemp <= dtemp + unsigned(din_buf) + offset;
dtemp1 <= to_integer(dtemp(17 downto 8));

My attempt is:

reg [17:0] dtemp;
reg signed [17:0] din_buf;
integer dtemp1;
parameter [17:0] offset = 18'b 000100000000000000;

din_buf <= {din[11], din[11], din[11], din[11], din[11], din[11], din};
dtemp <= dtemp + $unsigned(din_buf) + offset;
dtemp1 <= $signed(dtemp[17:8]);

My biggest problem is the VHDL "to_integer" designator, the closest I have come up with in Verilog is "$signed"

Any suggestions most welcome.

Cheers

Unless there is some valid reason for using an integer for dtemp1, I would probably just replace it with a reg type and try to avoid the reason for the conversion to begin with. I do not know how possible that it being I am not looking at all of the code.

 

Since most synthesis tools that I have worked with can convert either VHDL or Verilog to RTL, why would you want to risk 'breaking' hardware by trying to convert it from one HDL to another? I am not stating you don't have a valid reason for doing so, which is why I am posing the question before trying to answer the primary question.

Hi, thanks for the reply. I am using open source RTL tools like yosys etc, and as far as I am aware, it does not understand VHDL. Also I prefer to keep all my work in Verilog for personal reasons.

 

So , are you able to give a code example of how to change the code above not to use "Integer" but keep the signed/unsigned as intended by the VHDL code?

Thanks

 

So , are you able to give a code example of how to change the code above not to use "Integer" but keep the signed/unsigned as intended by the VHDL code?

Thanks

The following VHDL will do the same thing as the original VHDL and should be a lot easier to convert to Verilog:



You may want to verify I made no mistakes in the original VHDL to this VHDL code, but I think I have it correct.

Also, technically you don't need dtemp1, it is not doing anything, it is just a wire so to speak. use tdemp directly.

 

Many Thanks, will try that ..

 

Many Thanks, will try that ..

Not sure if you have a synthesis tool for VHDL but if you do, I would recommend converting it to RTL with the tool, then compare the RTL from that with the RTL you get from your Verilog conversion. They should match or be very close if you got the conversion correct. If you could run simulation on both that would be even better.

 

https://www.edautils.com/vhdl2verilog.html

 

You can cross-check with a VHDL to Verilog converter with syncad.