Hello Everyone,

I am not sure if this is a good place to post the thread, so if there is a better sub-forum that would be great.

The Internet is replete with resources that discuss 'proper' AGND and PGND connection strategies for a buck converter or other converter topologies. Overall, I see 3 suggestions:
1. AGND and PGND pins/balls are not connected at all.
2. AGND and PGND pins/balls are separated and only connected at an inner layer; e.g., PGND plane on L1&L2 and AGND pins/balls to L3 or L4 where it is finally connected to PGND.
3. AGND and PGND are immediately connected together; e.g., PGND plane on L1&L2 with AGND pin/balls connected to PGND together on L2

There is a great consternation on what is Good and Proper™. The engineering answer is "it depends" to which I agree. However, what I am hoping for is someone, an IC designer or other engineering expert, that can help clarify some additional questions. A good example of these questions is from the following thread on TI's forums posted by user Anthony Marini.

https://e2e.ti.com/support/power-ma...6-question-regarding-separating-pgnd-and-agnd

I have a good grasp of identifying the hot and cold loops of a converter, idealized component placement (input/output caps), traces are tight loops to minimize parasitic inductance in the return path, perhaps even fencing/slotting to keep currents circulating where desired. The missing piece is actually having a better understanding of the actual IC itself and how AGND/PGND are connected internally on the die. "Read the datasheet" or "only the IC designer knows" and you would be correct, but that is the question I am hoping someone with first hand knowledge can help address.

Is there someone, perhaps you yourself are an IC designer, that can provide an example of why AGND/PGND were required to be connected a certain way on the PCB to help kick off a discussion. What is it that pertains to the actual IC die design that will help dictate how to connect AGND and PGND on the PCB?

 

The AGND and PGND (or DGND) connections (both internal and external) are designed so the currents generated by the digital switching only go through the PGND and not through the AGND, as they can generate noise or errors in the analog circuitry.
So you look at what's generating any digital ground currents and try to direct them to go through the PGND only.

Once I had a problem with a 16-bit DAC (this was way back when, where it was a module using discrete parts) which was being used for equipment self-check calibration.
There was a small error in the analog output for certain sequences of bits.
After some trouble-shooting with a high accuracy digital voltmeter, I was able to determine that it was from some small digital currents generated internally coming out of the analog ground that were causing a several LSB error in the analog output voltage due to those currents through the PCB ground trace resistance.
The problem was solved by soldering a piece of bare copper wire along the top of the trace to lower its resistance.

So the problem was caused by the DAC design not keeping all the digital currents out of the analog return.
Of course, keeping all the digital ground currents out of the analog ground may be easier said than done.

 

Most datasheets have recommended board layouts for analog/digital lines and grounds.
https://forum.allaboutcircuits.com/threads/super-moon-shine.100322/post-898360


I used the TI layout instructions (layout.pdf) to make this ADC moonlight monitor board.

 

The AGND and PGND (or DGND) connections (both internal and external) are designed so the currents generated by the digital switching only go through the PGND and not through the AGND, as they can generate noise or errors in the analog circuitry.
So you look at what's generating any digital ground currents and try to direct them to go through the PGND only.

At surface level, yes. I think everyone is in agreement that PGND/DGND switching/noisy currents and quiet AGND currents should immediately return back to their respective grounding pins. But this reveals the insidious nature of Good and Proper PCB design.

For example, the TPS55330 datasheet shows the AGND pin and the PGND pins immediately connected to the power pad on layer 1; with some other notes of how to connect external components to AGND on an inner plane.


This connection scheme is also true for the RAA211250 from Renesas. AGND is immediately connected to the thermal pad just like PGND.


A third example from TI is the TPS6521905 which adamantly states not to connect AGND and PGND at the thermal pad, but at an inner plane.


Unfortunately, I have not found an example device where AGND and PGND are completely separate save maybe at the supply connector only.

Clearly there is something with the actual silicon die that drives each manufacture to be specific to the recommend connection whatever it may be. That is what I am hoping to understand better.[/quote][/QUOTE]

 

Clearly there is something with the actual silicon die that drives each manufacture to be specific to the recommend connection whatever it may be.

Latchup?
There was an old Unitrode app note which mentioned something along the lines, that ground noise could trigger a latchup mechanism.

 

I worked with a board that had an A/D converter with separate AGND and DGND pins, and an analog and digital ground plane that was split along the center of the package. The AGND was connected to the analog ground plane and the DGND to the digital ground plane.
The only connection tying the analog and digital grounds together was then made on the PCB near the A/D package.
The connection between the two was made with a ferrite bead to minimize the transfer of any high frequency noise between the two planes.

 

I design PCB's and not the Die in the parts, but I can say I agree with the TS engineering comment, "It Depends." In the 30+ years of design, I've done many SMPS and related circuits and each seems to have their own special sauce for design recommendations. A good friend of mine, Rick Hartley does classes at places like PCB West and others and covers this subject, (and others) in several of them. One thing that stands out from some of his talks are that App notes from manufactures should not be trusted until verified. He's not saying they don't know what they are doing, he saying that each design will have its own needs and sometimes App notes just don't cover your design issues. Examples I've see are the vendor app note says to place parts and planes like such. What you need to know is, is there board stackup the same as yours, do they place in their optimal placement but you can't due to one of those dang mounting holes mechanical wants due to shock and Vib requirements? So it is somewhat of a It Depends answer but I can say that typically, If I make sure I understand input current loop and output current loops and stray capacitance and inductance, etc. to keep said loops from sharing return current paths, I've done good. Having a common tie point between the grounds/returns has only been an issue on a few designs, most others have a single return for both and as I said, as long as I keep the current returns from crossing or mixing, I haven't had or at least my engineers have not complained about noise or other issues. Indeed a slit or gap, if small, can help but with some of the really fast switchers, I don't want a slot antenna either. That said, I'm not perfect and I've had a few that were not stellar performers, but they either were OK and didn't change or a component change or two was able to save a re-spin of the board. Your Mileage may very...

 

. One thing that stands out from some of his talks are that App notes from manufactures should not be trusted until verified. He's not saying they don't know what they are doing, he saying that each design will have its own needs and sometimes App notes just don't cover your design issues. Examples I've see are the vendor app note says to place parts and planes like such. What you need to know is, is there board stackup the same as yours, do they place in their optimal placement but you can't due to one of those dang mounting holes mechanical wants due to shock and Vib requirements?

This part is also very frustrating. Everyone has a good idea of component placement to minimize loops on a 2D top plane, but the moment you have different layer boards, multiple layer via connected layers, and then stack up on top of that, it adds a variable where it is very difficult to analyze. Some companies have the field solvers to help visualize this, others do not. IC vendors will say "here is our board; use it as an example". Well, ok, but when you have other parts from that same IC manufacturer (analog, digital, power, RF) or other IC vendors on the same board it is very easy to have competing interests which leads to endless discussions and debate. Everyone wants to sprinkle their own floobydust (RIP RAP).

So it is somewhat of a It Depends answer but I can say that typically, If I make sure I understand input current loop and output current loops and stray capacitance and inductance, etc. to keep said loops from sharing return current paths, I've done good. Having a common tie point between the grounds/returns has only been an issue on a few designs, most others have a single return for both and as I said, as long as I keep the current returns from crossing or mixing, I haven't had or at least my engineers have not complained about noise or other issues. Indeed a slit or gap, if small, can help but with some of the really fast switchers, I don't want a slot antenna either. That said, I'm not perfect and I've had a few that were not stellar performers, but they either were OK and didn't change or a component change or two was able to save a re-spin of the board. Your Mileage may very... \

There are tools that can extract the lumped R-L-C of defined nodes, and also calculate current densities throughout the board. I don't know why this isn't standard practice to help identify these concerns. Maybe it is, and I am just not that close enough to it.

The IC should be robust just as well as the PCB. The biggest unknown, and only the IC designers will know for sure, is understanding how the level shifters, and another analog are connected to the power FETs and output drivers (for converters). I would not trust the simplified schematic in any datasheet. I presume it is just as similar with mixed-signal designs with ADCs and DACs.

 

I worked with a board that had an A/D converter with separate AGND and DGND pins, and an analog and digital ground plane that was split along the center of the package. The AGND was connected to the analog ground plane and the DGND to the digital ground plane.
The only connection tying the analog and digital grounds together was then made on the PCB near the A/D package.
The connection between the two was made with a ferrite bead to minimize the transfer of any high frequency noise between the two planes.

How well did that actually work? I've always wondered if it was worth the effort.

 

How well did that actually work? I've always wondered if it was worth the effort.

It kept the digital noise out of the 12-Bit A/D, so the output digital word noise-dither was within the noise spec of the converter.

Actually, the original board had digital noise significantly above spec (at least two LSBs were jittering as I recall), and so I was asked to troubleshoot it.
I found I had to redesign the board since there was an error in the board layout that connected one of the ground pins to the incorrect ground (don't now remember which).
Routing it to their proper ground solved the problem.

So I guess whether it's worth the effort depends upon how concerned you are with digital ground noise getting into any analog signals.
I would think it certainly would be for any A/D converter of 12-bits or more.