Control 16 outputs using 4 inputs

Thread Starter

pirikitoman

Joined Jul 23, 2020
3
Hello everyone.
I need to control 16 output pins using only 4 inputs (bits). For example, if I need 3 outputs in the high state, the digital signals on my inputs are 0 0 1 0.
I also attach the true table below.
Maybe exists some commercial solution with similar behavior?
ThanksScreenshot from 2020-07-23 22-18-00.png
 

WBahn

Joined Mar 31, 2012
26,398
That gives one output per address input.
He wants all the outputs below that also energized.
That can be done with a bank of 15 OR gates to cascade the single HI output to all of the lower order outputs. This causes quite a bit of latency for the lowest order bit. This can be reduced by increasing the number of gates. I think you can cut the latency roughly in half at the cost of using about 50% more gates. You can also use multi-input OR gates to help out, too. A wired-OR approach could also be used.
 

Deleted member 115935

Joined Dec 31, 1969
0
CPLD is a relatively normal answer to this, 22V10 ? but you would need the environment, such as the programmer.

"logic chip " solution could be 16 , 4 input and gates, ( Two in each of the HC21, so 8 chips ) , and 4 inverters , to produce the compliment of each of the four inputs.
Then wire the correct true or compliment to each and gate.

So if your inputs are DCBA ( D msb A lsb )

output bit Q0 , you connect to its and gate /D /C /B /A

output bit Q1, you connect to its and gate /D /C /B A
output bit Q2, you connect to its and gate /D /C B /A
output bit Q3, you connect to its and gate /D /C B A

output bit Q15, you connect to its and gate D C B A


obviously , you can invert bits , so use a NAND gate not a AND gate, and change the inputs to each gate to compensate.
 

WBahn

Joined Mar 31, 2012
26,398
CPLD is a relatively normal answer to this, 22V10 ? but you would need the environment, such as the programmer.

"logic chip " solution could be 16 , 4 input and gates, ( Two in each of the HC21, so 8 chips ) , and 4 inverters , to produce the compliment of each of the four inputs.
Then wire the correct true or compliment to each and gate.

So if your inputs are DCBA ( D msb A lsb )

output bit Q0 , you connect to its and gate /D /C /B /A

output bit Q1, you connect to its and gate /D /C /B A
output bit Q2, you connect to its and gate /D /C B /A
output bit Q3, you connect to its and gate /D /C B A

output bit Q15, you connect to its and gate D C B A


obviously , you can invert bits , so use a NAND gate not a AND gate, and change the inputs to each gate to compensate.
How is that going to produce the truth table the TS is seeking?

For instance, if all four inputs are HI, the TS wants ALL sixteen outputs to be HI. Your solution would ONLY make output Q15 HI and all others LO.
 

Deleted member 115935

Joined Dec 31, 1969
0
How is that going to produce the truth table the TS is seeking?

For instance, if all four inputs are HI, the TS wants ALL sixteen outputs to be HI. Your solution would ONLY make output Q15 HI and all others LO.

Dahh ! Your dead right,
teach me to type first , think second...

Thank you,

So go back to using a CPLD, wonder how many terms the most complex would need ?
 

crutschow

Joined Mar 14, 2008
27,945
It's overkill, but you could also use a 16-bit (output) PROM.
Each of the first 4-bit address memory locations would contain the desired 16-bit output.
The latency is then the same for all address values.

But unless speed is a problem, I like WBahn's suggestion to cascade OR gates at the output of a 74154.
 

Deleted member 115935

Joined Dec 31, 1969
0
It's overkill, but you could also use a 16-bit (output) PROM.
Each of the first 4-bit address memory locations would contain the desired 16-bit output.
The latency is then the same for all address values.

But unless speed is a problem, I like WBahn's suggestion to cascade OR gates at the output of a 74154.
I like the cascaded or gate suggestion,

if propagation delay is a concern, at the expense of more logic, this could be for you

https://www.researchgate.net/figure/Binary-to-thermometer-decoder_fig2_258606371
 

Thread Starter

pirikitoman

Joined Jul 23, 2020
3
Thank you all very much guys!
You gave me great ideas!
For the project, I can not use a microcontroller or memory, so the best way is to design the custom decoder.
 
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