Hey there,

How can I construct an internal clock in a left-shift register, such that with every clock pulse, the digit on the rightmost end shifts to the one on its left and so on.

My approach for solving this problem is that making use of the "data-out" (the leftmost output), then transforming its value to a logic 1 and then connecting it back to each stage of the register, thus acting as a clock (with no outer clock input). I'm not so sure whether this actually works or not so please any suggestions or any help would be appreciated.

Thank you

 

It works fine as long as you have a valid RESET condition, and there is a recovery from any illegal states that might arise.

 

It works fine as long as you have a valid RESET condition, and there is a recovery from any illegal states that might arise.

Sorry for being ignorant but I'm new at this, how do you implement such a recovery function? D-flip flop??

 

A simple example. Suppose that you have 4 D-FlipFlops which can represent a total of 16 states. Suppose you have a counter or a state machine that uses only 12 of the 16 states. This means there are 4 states which have no meaning. You build a decoder with an output which is true for and of the 4 invalid states. The output of the decoder can be used to return the 4 D-FlipFlops to a valid state.