I am doing a 2-sided PCB with a TO-263 (the surface mount version of the TO-220). I want to use both sides of the PCB to lower the thermal resistance for the TO-263. To do this, I need vias between the areas of copper on the 2 sides of the board.

Now for the questions...

1) What size holes do I use for the vias?

2) How many vias and where do I place them relative to the TO-263?

3) Does it make sense to increase the area from 1.0 square inch to, say, 2 square inches to reduce thermal resistance?

4) Would using 2 oz. copper, instead of 1 oz. copper, make much difference in thermal resistance?

 

I am doing a 2-sided PCB with a TO-263 (the surface mount version of the TO-220). I want to use both sides of the PCB to lower the thermal resistance for the TO-263. To do this, I need vias between the areas of copper on the 2 sides of the board.

Now for the questions...

Throwing out some thoughts -- not definitive answers. There may well be countervailing considerations that I'm not taking into account.

1) What size holes do I use for the vias?

I would imagine that minimum size vias would be desired since the thickness of the copper in the via walls should be largely independent of via size and so the smaller the hole the greater the vertical wall area (what you want) to the missing hole area (what you don't want but have to accept). Of course, this means more vias to get the same wall area, but the total missing hole area will still be less.

2) How many vias and where do I place them relative to the TO-263?

I would imagine that placing them spread out more or less evenly over the entire plate area is best. In particular, I would think you want them directly underneath the component -- provided that doesn't impact the solderability of the part to the pad -- so that the heat has the shortest route to travel to get to the other side.

As for how many, that I don't know. I would imagine there is an optimal number and can guess at what some of the considerations would be, but I suspect that the actual number is quite a bit different than the simple model I have in mind would yield.

3) Does it make sense to increase the area from 1.0 square inch to, say, 2 square inches to reduce thermal resistance?

Probably. The more area the better the ability to vent heat to the surroundings. The concern becomes the solderability as you have to bring a larger area up to the soldering temperature. Putting solder relief slots around the part may become necessary but of course they work against the whole idea of what you are trying to accomplish.

4) Would using 2 oz. copper, instead of 1 oz. copper, make much difference in thermal resistance?

To the degree that you need to spread the heat out laterally to the larger plate area I would think it would have quite an impact. I doubt it would cut in in half, but it would probably reduce it quite a bit.

 

How is the part to be soldered?

 

How is the part to be soldered?

For the prototypes I will be hand soldering -- with a big soldering iron. Reflow later on.

 

I would imagine that minimum size vias would be desired since the thickness of the copper in the via walls should be largely independent of via size and so the smaller the hole the greater the vertical wall area (what you want) to the missing hole area (what you don't want but have to accept). Of course, this means more vias to get the same wall area, but the total missing hole area will still be less.

Makes sense.

I would imagine that placing them spread out more or less evenly over the entire plate area is best. In particular, I would think you want them directly underneath the component -- provided that doesn't impact the solderability of the part to the pad -- so that the heat has the shortest route to travel to get to the other side.

I don't think vias out at the edges would help much since the heat has to flow a long distance through thin copper to get there. Am I wrong?

As for how many, that I don't know. I would imagine there is an optimal number and can guess at what some of the considerations would be, but I suspect that the actual number is quite a bit different than the simple model I have in mind would yield.

A head scratcher to me, as well.

Probably. The more area the better the ability to vent heat to the surroundings. The concern becomes the solderability as you have to bring a larger area up to the soldering temperature. Putting solder relief slots around the part may become necessary but of course they work against the whole idea of what you are trying to accomplish.

I guess my question is: At what increase in area does the lateral thermal resistance offset the advantage of the larger area?

The thermal relief for solderablity problem is one I have faced in the past and (mostly) ignored. I kept the thermal relief since a lot of dissipation was not needed. I am now thinking that the thermal relief is less critical in SMD parts since the board is pre-heated before the solder is reflowed. What do you think?

To the degree that you need to spread the heat out laterally to the larger plate area I would think it would have quite an impact. I doubt it would cut in in half, but it would probably reduce it quite a bit.

That is what I was thinking as well. The tradeoff is that narrow traces are going to be harder to etch. The smallest pad pitch is 50 mils in this design so I doubt this is a problem, though. For the prototypes, I am stuck with 1 ounce copper (I think) for Advanced Circuits Barebones boards.

 

It has been some years since I went looking for info on this topic, and never found anything I considered to be very satisfactory. Much of it was rather hand wavy and lacking in sufficient carefully collected comparative data to be definitive. Some of the better info was written with regard to power ICs rather than discrete components. Some of what I have seen is just completely silly, such as recommendations for arrays of vast numbers of thermal feedthrough vias for parts that dissipate a fraction of a watt. Somehow putting the part in a QFN with an exposed thermal pad seemed to make thermal management far more critical than for the same part in an SO or other leaded package - silly.

With many modern power ICs the recommendation is to put an array of vias under the thermal pad on the part (no other choice with legs on at least two sides and often four). This is not without its drawbacks. The vias will "suck" solder from the joint between the pad and the foil. Capping the vias with soldermask on the opposite side of the board generally isn't workable since it causes gas entrapment that is very detrimental during reflow. Putting soldermask very close to the vias without actually covering them is a compromise that at least prevents solder from flowing freely to the foil around the vias. Lead free solder is such horrible stuff it doesn't flow all that well at the best of times.

In most cases, some loss of solder from the joint is not a big problem anyway. It is common to "window pane" large openings in solder paste stencils anyway, partly to limit the amount of solder and partly to keep the squeegee from scooping solder out instead of applying a uniform thickness. A TO-263, in my experience, would typically be done as four panes, but I don't remember the fraction of total area left open (my assembly house procured the stencil and had such things done to suit their process).

I have used, with seemingly good results, a "U" of vias just far enough from the tab end and sides of a TO-263 to allow a bit of solder mask between. If an area of copper without mask is used around the part, you can have another problem with solder not staying where it should be and flowing out of the joint area to the surrounding copper. I don't recall for certain, but I think I used vias of about 0.015 inches spaced at 0.05 inches. If you space them too close you lose more of the web between each pair of vias, and that web is necessary for lateral heat spreading.

Two ounce copper is better than one once copper, but not twice as good. I've used four ounce copper a lot, but not for surface mount - it makes for difficult problems with finer pitches.

The reality is that there is an assumption of four layer boards for surface mounted power parts. The other reality, in my opinion, is that surface mount sucks for thermal management.