Hi, I’d like us to analyse this circuit together, which simulates a ‘hard reset’.

The input Vi is a button that is held down for approximately 5 seconds.
The output Vout1 remains high for the entire duration that the button is pressed.
The input out1Filt to the second comparator is an RC circuit with a time constant of 4.2 seconds che si carica tramite R4 e C1//C2, which is compared with a resistive divider (set to 0.7) on the "+" input of the second comparator.

In theory, I would like Vout2 to switch after RC = 4.2 seconds.

R5 is there to allow the capacitors to discharge over the next few minutes.

The comparator is chosen at random; we can assume it is ‘ideal’ – I just want to understand the circuit.





1) Look the input out1Filt .. after 3.2 seconds it reaches 13V... but why doesn’t it reach 15.2V (0.63 × 24V) after R*C = 4.2 seconds?

2) In theory, the discharge (controlled by R3 and D1) should be much faster than the charge, but that doesn’t seem to be the case from the drop in input out1Filt

So, is the circuit not working as it should, or have I just got the dimensions wrong?

 

hi andrew,
It appears that the V(outfilt) never exceeds the V(thresh)...??
E

 

hi andrew,
It appears that the V(outfilt) never exceeds the V(thresh)...??
E
View attachment 367371

That's true... but how does it switch the second comparator, then?

 

Look the input out1Filt .. after 3.2 seconds it reaches 13V... but why doesn’t it reach 15.2V (0.63 × 24V) after R*C = 4.2 seconds?

The out1Filt voltage is limited to 1/2 * V3 + 0.7V ~ 12.7V because of the discharge path.

In theory, the discharge (controlled by R3 and D1) should be much faster than the charge, but that doesn’t seem to be the case from the drop in input out1Filt

The discharge path is kind of useless. As soon as out1Filt goes below ~ 12.7V the diode D1 in the discharge path closes and C1/C2 are discharged by R4||R5.

 

The discharge path is kind of useless. As soon as out1Filt goes below ~ 12.7V the diode D1 in the discharge path closes and C1/C2 are discharged by R4||R5

I don't understand this sentence; you say it's useless, but then you say D1 in the discharge path closes, so is it necessary(?)
Can you explain again?

Once the discharge path is removed, it reaches the threshold, but I still don’t understand why the output V(out2) doesn’t switch.. it seems to be following its own course

 

The out1Filt voltage is limited to 1/2 * V3 + 0.7V ~ 12.7V because of the discharge path.

OK, so it should be limited to 12.7V… but why there are 13V in the simulation (red line)?

 

I don't understand this sentence; you say it's useless, but then you say D1 in the discharge path closes, so is it necessary(?)
Can you explain again?

Sorry, that's an unfortunate error on my part. Of course it should say "opens" and not "closes". D1 is going high impedance as soon as out1Filt drops below ~12.7V. The discharge path doesn't work anymore as soon as that happens. R4/R5 are responsible for discharging C1/C2 and that takes even longer than charging those two caps.

Once the discharge path is removed, it reaches the threshold, but I still don’t understand why the output V(out2) doesn’t switch.. it seems to be following its own course

Why do you say V(out2) doesn't switch? It goes low when V(out1Filt) exceeds the ca. 5V threshold voltage V(thresh) of U2 and is back high again when V(out1Filt) drops below V(thresh).

You are trying to set V(thresh) to ca. 16.8V but that exceeds the input common voltage range (-0.1V up to Vcc-1.2V) of the comparator U2 by a large margin. U2 is supplied with Vcc=5V and the (+)/(-) inputs have ESD protection diodes connected to Vcc which limits V(thresh) to a value close to 5V.

Another problem is the 24V supply voltage for U1. Maximum supply voltage for both comparators is only 6V. Probably nothing to be concerned about in simulation but in real life U1 won't survive.

OK, so it should be limited to 12.7V… but why there are 13V in the simulation (red line)?

For simplicity's sake I left out R3 which is in series with D1. There is a small, additional voltage drop (0.3V seems reasonable) across R3.

 

Sorry, that's an unfortunate error on my part. Of course it should say "opens" and not "closes". D1 is going high impedance as soon as out1Filt drops below ~12.7V. The discharge path doesn't work anymore as soon as that happens. R4/R5 are responsible for discharging C1/C2 and that takes even longer than charging those two caps.



Why do you say V(out2) doesn't switch? It goes low when V(out1Filt) exceeds the ca. 5V threshold voltage V(thresh) of U2 and is back high again when V(out1Filt) drops below V(thresh).

You are trying to set V(thresh) to ca. 16.8V but that exceeds the input common voltage range (-0.1V up to Vcc-1.2V) of the comparator U2 by a large margin. U2 is supplied with Vcc=5V and the (+)/(-) inputs have ESD protection diodes connected to Vcc which limits V(thresh) to a value close to 5V.

Another problem is the 24V supply voltage for U1. Maximum supply voltage for both comparators is only 6V. Probably nothing to be concerned about in simulation but in real life U1 won't survive.



For simplicity's sake I left out R3 which is in series with D1. There is a small, additional voltage drop (0.3V seems reasonable) across R3.

Hi, and thanks for your reply.

I’ve realised myself that I made a mistake in the circuit; I’d been powering the second comparator with 5V… but it actually needs 24V. Sorry for the oversight.
Now that I've set the button press duration to 8 seconds, everything seems to be working (I've disconnected the diode discharge path)



I don't understand why there is an 'offset' of 1.16V on Vout1Filt (as shown in the image) ... shouldn't it be 0?

 

Hi andrew,
This edited circuit shows the origin of the +1.00v.
E

 

Hi andrew,
This edited circuit shows the origin of the +1.00v.
E
View attachment 367401

Hi, I gather that the source is the second U2 stage, but why do you think that is?

 

hi andrew,
There is approx 16V difference between the OPA Inv and NInv inputs which is creating a 5uA current out of the Inv pin, which develops a 1V across the 210K.
I am not sure if the is is due to the LTSpice LT1720 model, or if it would happen an actual circuit???
E

 

I don't understand why there is an 'offset' of 1.16V on Vout1Filt (as shown in the image) ... shouldn't it be 0?

There's a small bias current, up to 6uA according to the datasheet, flowing out of the (-) input of U2 and through R4 || R5 ( ~200k).

 

hi andrew,
There is approx 16V difference between the OPA Inv and NInv inputs which is creating a 5uA current out of the Inv pin, which develops a 1V across the 210K.
I am not sure if the is is due to the LTSpice LT1720 model, or if it would happen an actual circuit???
E
View attachment 367404

There's a small bias current, up to 6uA according to the datasheet, flowing out of the (-) input of U2 and through R4 || R5 ( ~200k).

In the end, to discharge it quickly, I should have connected the diode’s cathode to the op-amp’s output—not to the input of the resistor divider.

 

In the end, to discharge it quickly, I should have connected the diode’s cathode to the op-amp’s output—not to the input of the resistor divider.

Yes, a diode with an additional series resistor if you want to control discharge time. Connect that across R4.

 

? are you sure about the +24V supply - 1-stly because of https://www.analog.com/media/en/technical-documentation/data-sheets/17201fc.pdf#page=2 , 2-dly because of several todays comparators are cmos with working voltage ranges below the 18 16 V
however the old https://www.ti.com/lit/ds/symlink/lm193-mil.pdf#page=4 can coupe with such . . .

other than this tiny potential technical issue ::

you need to envision the entire process from power up to power down

• the output states should preferedly be --or-- reach their initial states ASAP after power ON
• you may need to address the "dummy user" flickers with the RESET button rather than presses it 5s and then waits for minutes after retry
• you may expect the RESET button is toggled (altered) at OUT.2 outputting a valid active RESET state

which defines certain requirements ::

• the delay timing must be reset at each button release . . . like fast?
• the reset button may be allowed/enabled only when the sys is not in a reset routine or at a critical phase of it !!!
• the "down- (control-) flow" propagation of the OUT.2 reset must be enabled only when after power -up the sys is at a valid state
• ??? if the RESET button is being held down indefinitely it should not retrigger the OUT.2 twice
• . . . there maybe more

each device trends to a certain output state at initial supply ramp at power up - it may be that the different modules (functional blocks) of the system need to be timed for overall order in which they "boot up" their power . . .

however if you need a 4.2s delay for button pressed state . . . fast improvising the Falstad sim of . . . RESET button module

 

Hi, I’d like us to analyse this circuit together, which simulates a ‘hard reset’.

The input Vi is a button that is held down for approximately 5 seconds.
The output Vout1 remains high for the entire duration that the button is pressed.
The input out1Filt to the second comparator is an RC circuit with a time constant of 4.2 seconds che si carica tramite R4 e C1//C2, which is compared with a resistive divider (set to 0.7) on the "+" input of the second comparator.

In theory, I would like Vout2 to switch after RC = 4.2 seconds.

R5 is there to allow the capacitors to discharge over the next few minutes.

Hi, I’d like us to analyse this circuit together, which simulates a ‘hard reset’.

The input Vi is a button that is held down for approximately 5 seconds.
The output Vout1 remains high for the entire duration that the button is pressed.
The input out1Filt to the second comparator is an RC circuit with a time constant of 4.2 seconds che si carica tramite R4 e C1//C2, which is compared with a resistive divider (set to 0.7) on the "+" input of the second comparator.

In theory, I would like Vout2 to switch after RC = 4.2 seconds.

R5 is there to allow the capacitors to discharge over the next few minutes.

The comparator is chosen at random; we can assume it is ‘ideal’ – I just want to understand the circuit.
View attachment 367368

View attachment 367369


1) Look the input out1Filt .. after 3.2 seconds it reaches 13V... but why doesn’t it reach 15.2V (0.63 × 24V) after R*C = 4.2 seconds?

2) In theory, the discharge (controlled by R3 and D1) should be much faster than the charge, but that doesn’t seem to be the case from the drop in input out1Filt

So, is the circuit not working as it should, or have I just got the dimensions wrong?

The comparator is chosen at random; we can assume it is ‘ideal’ – I just want to understand the circuit.
View attachment 367368

View attachment 367369


1) Look the input out1Filt .. after 3.2 seconds it reaches 13V... but why doesn’t it reach 15.2V (0.63 × 24V) after R*C = 4.2 seconds?

2) In theory, the discharge (controlled by R3 and D1) should be much faster than the charge, but that doesn’t seem to be the case from the drop in input out1Filt

So, is the circuit not working as it should, or have I just got the dimensions wrong?

Hello,

If you want to understand the way this circuit works then you have to decide on a particular kind of comparator. There are two basic types: open collector output and just with a regular output.
The regular output type might be rail to rail or something less, but the open collector output needs a pullup so that enters into the operation by a large amount.

The one used for this example is the LT1720 and that seems to have a rail to rail output so you don't need a pullup.
It does however have a power supply limit of 7v so 24v is far too high for it. It may still work in the simulator though. Let's assume it does.

The formula for a charging or discharging capacitor with initial voltage is:
V=(E*R2)/(R2+R1)-((E*R2-v*R2-v*R1)*e^(-t/(C*R2)-t/(C*R1)))/(R2+R1)

and for your circuit (with the diode part removed and V is the voltage at the second comparator input) is:
V=(E*R5)/(R5+R4)-((E*R5-v*R5-v*R4)*e^(-t/(C*R5)-t/(C*R4)))/(R5+R4)

This gets a little simpler if we define:
R45=R4+R5, and
A=(R4+R5)/(R4*R5*C)

then we can write it as:
V=(E*R5)/R45-(e^(-t*A)*(E*R5-v*R5-v*R4))/R45

To use that formula, replace R4 and R5 in the expression and in R45 and A, then set v equal to the initial capacitor voltage and set E equal to the output voltage of the comparator. Assume for charging the output of the comparator E is +Vcc and for discharging the output of the comparator E is zero volts (0v). You then look for the time that the filter output reaches the set voltage of the second capacitor on the noninverting input.

The time to reach the set point is (log here is the natural log ln):
t=-(log(E*R5-Vset*R45)-log((E-v)*R5-v*R4))/A

The diode and resistor do not make too much sense though so it was removed. If you need hysteresis for the first comparator, add it in the more typical way with a resistor from the comparator output to the comparator noninverting input like you did for the second capacitor.

If you do want to keep that diode and series resistor in the circuit, the analysis will get a little more complicated. We can do that too though if you like.

 

? are you sure about the +24V supply - 1-stly because of https://www.analog.com/media/en/technical-documentation/data-sheets/17201fc.pdf#page=2 , 2-dly because of several todays comparators are cmos with working voltage ranges below the 18 16 V
however the old https://www.ti.com/lit/ds/symlink/lm193-mil.pdf#page=4 can coupe with such . . .

other than this tiny potential technical issue ::

you need to envision the entire process from power up to power down

• the output states should preferedly be --or-- reach their initial states ASAP after power ON
• you may need to address the "dummy user" flickers with the RESET button rather than presses it 5s and then waits for minutes after retry
• you may expect the RESET button is toggled (altered) at OUT.2 outputting a valid active RESET state

which defines certain requirements ::

• the delay timing must be reset at each button release . . . like fast?
• the reset button may be allowed/enabled only when the sys is not in a reset routine or at a critical phase of it !!!
• the "down- (control-) flow" propagation of the OUT.2 reset must be enabled only when after power -up the sys is at a valid state
• ??? if the RESET button is being held down indefinitely it should not retrigger the OUT.2 twice
• . . . there maybe more

each device trends to a certain output state at initial supply ramp at power up - it may be that the different modules (functional blocks) of the system need to be timed for overall order in which they "boot up" their power . . .

however if you need a 4.2s delay for button pressed state . . . fast improvising the Falstad sim of . . . RESET button module

Hi, I used a generic comparator in the simulation because it’s still just a ‘simulation’… as I mentioned in the main post "The comparator is chosen at random; we can assume it is ‘ideal’ – I just want to understand the circuit"

 

? are you sure about the +24V supply - 1-stly because of https://www.analog.com/media/en/technical-documentation/data-sheets/17201fc.pdf#page=2 , 2-dly because of several todays comparators are cmos with working voltage ranges below the 18 16 V
however the old https://www.ti.com/lit/ds/symlink/lm193-mil.pdf#page=4 can coupe with such . . .

other than this tiny potential technical issue ::

you need to envision the entire process from power up to power down

• the output states should preferedly be --or-- reach their initial states ASAP after power ON
• you may need to address the "dummy user" flickers with the RESET button rather than presses it 5s and then waits for minutes after retry
• you may expect the RESET button is toggled (altered) at OUT.2 outputting a valid active RESET state

which defines certain requirements ::

• the delay timing must be reset at each button release . . . like fast?
• the reset button may be allowed/enabled only when the sys is not in a reset routine or at a critical phase of it !!!
• the "down- (control-) flow" propagation of the OUT.2 reset must be enabled only when after power -up the sys is at a valid state
• ??? if the RESET button is being held down indefinitely it should not retrigger the OUT.2 twice
• . . . there maybe more

each device trends to a certain output state at initial supply ramp at power up - it may be that the different modules (functional blocks) of the system need to be timed for overall order in which they "boot up" their power . . .

however if you need a 4.2s delay for button pressed state . . . fast improvising the Falstad sim of . . . RESET button module

??? if the RESET button is being held down indefinitely it should not retrigger the OUT.2 twice
Excellent point. Do you have any idea how we could modify or add to the current schematic to set an upper time limit as well?
For instance, the filter is currently set to 4–5 seconds… if I wanted to set a maximum press time of 10 seconds, after which an LED would light up (for example), how could I do that?

I’m always talking about ‘homework’, so let’s run some simulations in LTSpice and do the calculations by hand

Yes, a diode with an additional series resistor if you want to control discharge time. Connect that across R4.

Hello,

If you want to understand the way this circuit works then you have to decide on a particular kind of comparator. There are two basic types: open collector output and just with a regular output.
The regular output type might be rail to rail or something less, but the open collector output needs a pullup so that enters into the operation by a large amount.

The one used for this example is the LT1720 and that seems to have a rail to rail output so you don't need a pullup.
It does however have a power supply limit of 7v so 24v is far too high for it. It may still work in the simulator though. Let's assume it does.

The formula for a charging or discharging capacitor with initial voltage is:
V=(E*R2)/(R2+R1)-((E*R2-v*R2-v*R1)*e^(-t/(C*R2)-t/(C*R1)))/(R2+R1)

and for your circuit (with the diode part removed and V is the voltage at the second comparator input) is:
V=(E*R5)/(R5+R4)-((E*R5-v*R5-v*R4)*e^(-t/(C*R5)-t/(C*R4)))/(R5+R4)

This gets a little simpler if we define:
R45=R4+R5, and
A=(R4+R5)/(R4*R5*C)

then we can write it as:
V=(E*R5)/R45-(e^(-t*A)*(E*R5-v*R5-v*R4))/R45

To use that formula, replace R4 and R5 in the expression and in R45 and A, then set v equal to the initial capacitor voltage and set E equal to the output voltage of the comparator. Assume for charging the output of the comparator E is +Vcc and for discharging the output of the comparator E is zero volts (0v). You then look for the time that the filter output reaches the set voltage of the second capacitor on the noninverting input.

The time to reach the set point is (log here is the natural log ln):
t=-(log(E*R5-Vset*R45)-log((E-v)*R5-v*R4))/A

The diode and resistor do not make too much sense though so it was removed. If you need hysteresis for the first comparator, add it in the more typical way with a resistor from the comparator output to the comparator noninverting input like you did for the second capacitor.

If you do want to keep that diode and series resistor in the circuit, the analysis will get a little more complicated. We can do that too though if you like.

 

hi andrew,
As this is a homework project, please post a circuit or simulation on how you would modify the circuit, we can then talk you through it.
E

 

if you want to understand things, you need to read datasheet. as was already pointed out V2 need to be 5V to use this IC. this IC cannot work with 24V. if you want that, use different IC. if you lower V2 to 5V all of observed is null and void... for example input will never be more than 5.6V. so to make it work, the other two 24V sources would need to be reduced too.