Question
The question is Specify the W/L ratios for all transistors in terms of the ratios of n and p of the basic inverter, such that the worst case tphl and tplh of the CMOS gate are equal to the basic inverter.
My query
Okay guys, l am confused on coming up with the size for the transistor C and D in the PDN. Since l already said transistor B in the PDN has a size of 2n, does that mean automatically C and D which are in parallel with B also become 2n ?
Attempt to solution
See the attached PDF.
The question is Specify the W/L ratios for all transistors in terms of the ratios of n and p of the basic inverter, such that the worst case tphl and tplh of the CMOS gate are equal to the basic inverter.
My query
Okay guys, l am confused on coming up with the size for the transistor C and D in the PDN. Since l already said transistor B in the PDN has a size of 2n, does that mean automatically C and D which are in parallel with B also become 2n ?
Attempt to solution
See the attached PDF.
Attachments
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