Hello,I have following circuit


and I need to prove that this circuit has non-zero static dissipation.
Assume the inverter switches ideally at VDD/2, neglect body effect, channel length modulation and all parasitic capacitance.

Now When A=B= VDD, the voltage at node x is VX=VDD-VtN,but how can I prove analytically that there is no static power dissipation for inverter cmos? Because P=(Vdd^2)/Rp how can I compute equivalente resistance Rp for PMOS M2?

 

hi e2021,
As this is Homework we must see your best attempt at answering, we can then help.?
E

 

In this case M2 works in saturation or linear region?

 

I made my attempt to resolve it....any help to continue??

 

excuse me.....text error Now When A=B= VDD, the voltage at node x is VX=VDD-VtN,but how can I prove analytically that there is no zero static power dissipation for inverter cmos?

 

M2 PMOS works in velocity saturation
Rp=Vds/Idp=Vdsat/(k'p*(w/l)*Vdsat*(2.5-2.07-0.4)) and I neglet Vdsat/2
w/l=6 k'p=30*10^-6 Vdsat=1 V
Rp=185kOhm

Is it correct my way of thinking??
Please help me.

 

Any help??Please....

 

Are both transistors on at any time?

 

No....the logic function performed by this circuit is a NAND gate... any help??

 

What are the threshold voltages of M1 and M2?

 

threshold voltages of M1 and M2 ....please view image.....Vtn=0.43 and Vtp=-0.4...

 

any help????

 

Let's call the threshold 0.4 V. The gates are There is 1.25V of forward bias between each transistor's gate and source, so there is conduction overlap during most of the transition on the input.

That's as far as I can go as I have not studied MOSFETs in depth. The fellow who was helping you is a moderator here and will in all likelihood be aware of where you are with your problem and back to help you.

 

Hi e2021,
If possible, I would have helped you, but unfortunately, your query is not in my area of expertise.

E

 

:bump: