Hello -

Supply Voltage VDD = +12 v.
On a Circuit Board the design has one output of CD4023BD ( CMOS NAND ) driving two CMOS NAND inputs ( CD4011BD ) and driving two
simple Transistor Switch's , one NPN and one PNP ( one 2N2222 , one 2N2907 ).

Do you think the Fan Out of the CD4023BD can drive these 4 individual
circuit loads properly ?

Thank you
Any suggestions appreciated.

 

I suggest you post the datasheet of the CD4023BD using the "go advanced" button and the "manage attachments" feature.

 

Here is the datasheet for CD4023BD.

 

A lot of "ifs". If you give it 15 volts and if you keep it cool, it can give or take 6.8 milliamps if you are able to allow a loss of 1.5 volts inside the chip. If you look at the rest of the circuit, you can see if 6.8 milliamps is enough.

 

Well to let you know the output of CD4023BD in the previous mentioned configuration Died today or last night. Interesting that the past two days in the garage have been above high temperatures here in Raleigh, NC.

The supply is kept at + 12 volts.
Interesting that the Output Drive Current drops off at the Higher Temperatures within the Spec Sheet !

ANOTHER NOTE IS that about a week ago I temporarily added a low current
LED which has a built in Current limit resistor to the Output of this CD4023BD CMOS Nand Gate, I guess this didn't help stress this output neither.

Thanks for the replies . .
Thanks for letting me discuss this - pondering my own thoughts !

 

Hello -

I performed the current measurements on the circuit described at the Start
Of This Thread last night.
The measurements total 4.94 mA - which is at a garage temperature of 79
degree F. See [ ~ 6 mA - 4.94 mA ] = 1.06 mA does not leave very much
margin for error, component tolerance changes, temperature, noise, etc.

Is their anyone interested in looking at this circuit if I post
the actual circuit ?


Thanks Alot

 

A working circuit removes almost all the need for "margin for error". Margin is what is needed before you build it. After it's built and working properly, you're done.

Why do you have any doubts now?

and yes, posting the circuit always helps us answer you.

 

Hello # 12 -

I do have some doubts and concerns.
In circuit current measurements :
(1) My test equipment is not of the highest quality.
My current meter being a DVM has never been calibrated.
(2) Performing the measurements rather quickly, I resourced to
long ( relatively) wire lead length
(3) Adding a brief amount of Heat with Hair Dryer - I was able to
see the current increase with temperature.

A. My primary concern is that this board controls a very expensive tool.
B. This Circuit is not my Design - a companies design which has
since disolved, therefore, support for the board / documentation, etc.
is limited.

Can you provide some suggestions.
I appreciate.

 

Post a drawing of the circuit. Without that, it's all guesing.

 

Hello Again -

Attached File : A rough drawing of the Circuit.

I have included only the major important part of the circuit concerning the FAN OUT of CMOS NAND Gate CD4023BD.

You may have to scroll to the bottom of the .pdf attachment to view.

THANK YOU

 

In the circuit you posted, the heaviest load is the 10k resistor to the base of the PNP transistor; 1.2mA if Vdd=12v. The NPN transistor has a diode drop and a 330k resistor between the base and the output you're concerned about; that's only about a 35uA load. The inputs to the other CMOS gates have extremely high impedance, so they're virtually no load.

So, your total load on that output is around 1.235mA.

 

Hello -

I have posted the Circuit Diagram - see prior post.

Thanks

 

Any Help or suggestions would be appreciated.

I have this as a priority presently and it is on my workbench now.

Possibly some Book Reference Material Suggestions.
Thank you

 

Now that wookie has established that your circuit is very conservative and no danger to the chip or anyone else, what help do you want?

as for suggestions, I suggest that it works.

 

I have an idea that our OP doesn't realize that their thread now has a 2nd page.

And yes, thanks for pointing out that the circuit is conservative; I forgot to mention that.

 

I am still concerned I believe because the measurements that I took
are much different than what Sgt. suggested should be the current draw.
Possibly the way I took measurements is incorrect or their is something else wrong in associated circuits or something that we do not know.

The way : I lifted the PNP Transistors' Diode Anode and series read the
current. I lifted the 10K resistor and series read the current. I lifted one
of the other NAND GATE inputs and series read the current.
In total - adding the individual measurements I calculated 4.95 mA draw.
The 10 K was drawing ~ 3.4 mA , the PNP Diode was drawing ~ 1.5 mA -
per measurements.

The 2N2222 or 2N3907 Base Current when transistor is in Saturation or Cutoff per spec's maximum is 15 mA.
Yes the CMOS NAND GATE input current draw I know is in uA range -
I believe the spec reads +/- 1 uA.

Where do I go from here ?

Thank You for reply's Sgt. and # 12

Yes- I want to get this straightened out.

 

Now I understand a bit about the rough test setup I was using.
The wire length (as posted earlier) was long.
The wire length between multimeter and component leads was about
two feet long on each, the positive meter lead and the negative meter lead.
I would like to re-measure using shortest lead length.

Thank you

 

I would like to see what you have connected to the collector of the NPN, and to the emitter of the PNP.

 

Just FYI, the 2N2222 is an NPN transistor. The way you have the schematic drawn, that NPN's transistor has a 330k resistor and a 1N4935 diode between its' base and the output of the 3-input NAND gate.

12v / 330k = 36.363...uA, even if the 1N4935 diode were a dead short and the transistor base was shorted to ground, when the output of the NAND is high (at 12v). You say you're measuring 1.5mA from the NAND output to the diode, so something is definitely wrong - that's over 42 times as much current as it should be. Resistors usually either increase in value or open altogether; I do not recall ever seeing one go lower in value than its' markings, within the tolerance marked. So, either that 330k Ohm resistor is marked something different than 330k, your supply voltage is higher than 12v, or some other problem that I can't divine from this end.

Same with the 10k resistor. 12v/10k Ohms = 1.2mA. That's the MOST it could possibly be, when the output from the NAND is low; when it's high, the current draw should be practically nothing. Unless, of course, you misread the resistance of that 10k resistor, or the voltage supply is more than 12v, or some other error. Or, somehow the resistor is magically partially shorted, which is something that I've never seen happen.

 

Hello Sgt.

Thanks !
The board this circuit is present on is 26 - 30 years old.
The manufacturer and design company have disolved.
Anyway, I have experience a few MIB SHORTS on the two similiar
boards which I have. I believe the solder iron temperature which
I was first using created a couple Mib Shorts, one developed believed
when the owner over stressed a particular I/O Line.
It's hard to believe that Solder Iron Temperature is creating these MIB Shorts, however, that is what all indications and testing has proven
thus far. AGE of the board and Time Powered Up may contribute as well.

I define MIB SHORTS as internal individual circuit traces or nets which short internally to another circuit trace or net.
I do know that the CMOS NAND GATE output here in question had
a suspected mib short because with all components on this net lifted but the other NAND gate inputs the net was reading like 5.2 volts.
I don't think these CMOS Nand Gate inputs float or supply 5.2 volts
on their own, so their may be a Mib Short on this net.

With your Help and # 12's Help and thinking about this -
it may turn out to be the Mib problem at this circuit point.

I will look into the Mib Short possibility again soon.
I will post a response !
Thanks