I have an unused d flip flop(CMOS based) in my design, I have pulled down the inputs with a 30k resistor. I have also pulled down the outputs (q and qbar) with 30k resistors. The input will be permanently low as I have tied pulled them down to ground , the pmos transistor will be on and the output is pulled to VCC, however the 30k pull down resistor to ground should minimize the current drawn from VCC as it would be VCC /30k mA , could someone provide your input on this ?