CMOS discrete logic output pins

Thread Starter

sakthi1988

Joined Jul 3, 2020
6
I have an unused d flip flop(CMOS based) in my design, I have pulled down the inputs with a 30k resistor. I have also pulled down the outputs (q and qbar) with 30k resistors. The input will be permanently low as I have tied pulled them down to ground , the pmos transistor will be on and the output is pulled to VCC, however the 30k pull down resistor to ground should minimize the current drawn from VCC as it would be VCC /30k mA , could someone provide your input on this ?
 

jpanhalt

Joined Jan 18, 2008
9,755
Inputs are high impedance and low current. For example, the CD4017 inputs are uA; however, outputs are mA. Why pull down the outputs?
 

Irving

Joined Jan 30, 2016
815
Pulling down the outputs will increase power consumption and is unnecessary. There's no preference whether to pull inputs low or high, the leakage is 0.1uA either way, no resistor needed, however holding SET & RESET high will put Q and /Q high and should be the lowest power configuration though that's not defined.
 

Thread Starter

sakthi1988

Joined Jul 3, 2020
6
Pulling down the outputs will increase power consumption and is unnecessary. There's no preference whether to pull inputs low or high, the leakage is 0.1uA either way, no resistor needed, however holding SET & RESET high will put Q and /Q high and should be the lowest power configuration though that's not defined.
Thanks for the response , so can I leave the outputs floating (q and /q) , ?
 

MrChips

Joined Oct 2, 2009
21,350
Thanks for the response , so can I leave the outputs floating (q and /q) , ?
Wrong terminology.
Think of "floating" to mean "like an object allowed to bounce along with the waves".

Inputs float on their own. You need to prevent them from bouncing around.
Outputs don't float. Let them do their own thing. You leave them not connected to any load.

Another analogy, like your ears (input) and mouth (output).
You can block your ears when you don't want to hear but don't ever gag your mouth with a rag.
 

WBahn

Joined Mar 31, 2012
25,918
I have an unused d flip flop(CMOS based) in my design, I have pulled down the inputs with a 30k resistor. I have also pulled down the outputs (q and qbar) with 30k resistors. The input will be permanently low as I have tied pulled them down to ground , the pmos transistor will be on and the output is pulled to VCC, however the 30k pull down resistor to ground should minimize the current drawn from VCC as it would be VCC /30k mA , could someone provide your input on this ?
How will it minimize the current drawn from Vcc? Wouldn't 100 kΩ reduce it further? How much current would flow in the output if you removed the pulldown resistor alltogether?

You never want to leave logic inputs, particularly CMOS logic inputs, floating unless the specs specifically say that they are designed for it. If they aren't, they will be very susceptible to noise pickup, which can get conveyed into the other logic on the chip. It can also result in shoot-through which is when both output stages are turned on at the same time, which can result in damaging currents flowing in the device.

In general, whether you pull them HI or pull them LO depends on depends on which one makes sense. Sometimes it doesn't matter. You just need to consider what the logic device does.

In general, you want to leave unused outputs open. They will go to whatever level makes sense for their current inputs and then stay there fat, dumb, and happy. Connecting them to anything will only increase the static power consumption.
 

WBahn

Joined Mar 31, 2012
25,918
Pulling down the outputs will increase power consumption and is unnecessary. There's no preference whether to pull inputs low or high, the leakage is 0.1uA either way, no resistor needed, however holding SET & RESET high will put Q and /Q high and should be the lowest power configuration though that's not defined.
How do you figure that holding both the set and reset inputs HI will result in the lowest power consumption? That depends entirely on the internal design of the part. Many FF designs implement asynchronous set and reset inputs as designed contention in which the set/reset signal has to overdrive the storage node that is being held by the data latch, resulting in rather high consumption until the storage latch flips to match the input. If you assert both set and reset at the same time, that can prevent that from happening and thus result in sustained high current draw.
 

Thread Starter

sakthi1988

Joined Jul 3, 2020
6
How will it minimize the current drawn from Vcc? Wouldn't 100 kΩ reduce it further? How much current would flow in the output if you removed the pulldown resistor alltogether?

You never want to leave logic inputs, particularly CMOS logic inputs, floating unless the specs specifically say that they are designed for it. If they aren't, they will be very susceptible to noise pickup, which can get conveyed into the other logic on the chip. It can also result in shoot-through which is when both output stages are turned on at the same time, which can result in damaging currents flowing in the device.

In general, whether you pull them HI or pull them LO depends on depends on which one makes sense. Sometimes it doesn't matter. You just need to consider what the logic device does.

In general, you want to leave unused outputs open. They will go to whatever level makes sense for their current inputs and then stay there fat, dumb, and happy. Connecting them to anything will only increase the static power consumption.
Thanks for the response, true with no pull down resistors from the output pins, the static power consumption will be 0 mW. I will keep the unused outputs open .
 

Thread Starter

sakthi1988

Joined Jul 3, 2020
6
Wrong terminology.
Think of "floating" to mean "like an object allowed to bounce along with the waves".

Inputs float on their own. You need to prevent them from bouncing around.
Outputs don't float. Let them do their own thing. You leave them not connected to any load.

Another analogy, like your ears (input) and mouth (output).
You can block your ears when you don't want to hear but don't ever gag your mouth with a rag.
Thanks for the response , I won't connect the output to any load
 

Thread Starter

sakthi1988

Joined Jul 3, 2020
6
Thanks for the response, true with no pull down resistors from the output pins, the static power consumption will be 0 mW. I will keep the unused outputs open .
I meant 0mW for power consumption because of the pulled down resistor , of course the device will have static power consumption for operation
 

Irving

Joined Jan 30, 2016
815
How do you figure that holding both the set and reset inputs HI will result in the lowest power consumption? That depends entirely on the internal design of the part. Many FF designs implement asynchronous set and reset inputs as designed contention in which the set/reset signal has to overdrive the storage node that is being held by the data latch, resulting in rather high consumption until the storage latch flips to match the input. If you assert both set and reset at the same time, that can prevent that from happening and thus result in sustained high current draw.
I was wrong, in that it makes no difference, the CMOS part is totally symmetrical internally so it doesn't matter if all inputs are high or low as long as unused ones are tied directly to either Vcc or Gnd. For the CMOS 4013 holding S and R both high results in Q and /Q both being high which is a valid output state. It has no negative or positive impact on the quiescent supply current, since power is only consumed when changing state.

I was misremembering something from early ECL devices where low inputs (low i/p = 1uA, high i/p = 150uA) and low outputs were preferred and the devices were -ve logic so S & R both low = low Q and /Q outputs and lowest power consumption.
 

WBahn

Joined Mar 31, 2012
25,918
I was wrong, in that it makes no difference, the CMOS part is totally symmetrical internally so it doesn't matter if all inputs are high or low as long as unused ones are tied directly to either Vcc or Gnd. For the CMOS 4013 holding S and R both high results in Q and /Q both being high which is a valid output state. It has no negative or positive impact on the quiescent supply current, since power is only consumed when changing state.

I was misremembering something from early ECL devices where low inputs (low i/p = 1uA, high i/p = 150uA) and low outputs were preferred and the devices were -ve logic so S & R both low = low Q and /Q outputs and lowest power consumption.
What CMOS part? The TS never even said which CMOS family he is talking about, let alone a specific part within that family.

In the case of the CD4013, if you are trying to minimize power then if you tie both the set and the reset HI, you should also tie the data input HI, otherwise you will be charging and discharging the charge storage node for the master section on each clock cycle. If you assert just the reset, then you should tie the data line LO to avoid the same pumping behavior.

Asserting both the set and reset inputs should not just be done blindly, since having both outputs HI can have unintended consequences. In the case where the outputs truly are not being used, this is immaterial. But sometimes a FF is used within a design and an option is to effectively remove it from the design (such as when the same circuit is used for different products and the differences are controlled by disabling certain parts of the circuit). If this is the case, then having both outputs of a FF be HI can cause problems because some parts of the circuit might see that state as being a 1 (those using the Q output) and others might see it as being a 0 (those using the /Q output). But this falls under the guidance given earlier that the level that you tie unused inputs to should reflect the functionality of the circuit.
 

Irving

Joined Jan 30, 2016
815
In the case of the CD4013, if you are trying to minimize power then if you tie both the set and the reset HI, you should also tie the data input HI, otherwise you will be charging and discharging the charge storage node for the master section on each clock cycle. If you assert just the reset, then you should tie the data line LO to avoid the same pumping behavior
True, but if the FF is not being used you wouldn't want to route the clock to it as that will use power simply by charging/discharging the gates of the 6 or so internal clock buffers, irrespective of the other inputs. Unused inputs on a FF in use should be tied to either Vdd or Vss so as not to affect operation, ie for Set & Reset that would be ground, but if a whole FF isn't being used you'd tie all 4 inputs (including Clock) to whichever rail is easiest. The layout of a CD4013 makes Vss the logical choice, however tying some or all to Vdd is acceptable, it won't result in increased consumption.
 
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Thread Starter

sakthi1988

Joined Jul 3, 2020
6
What CMOS part? The TS never even said which CMOS family he is talking about, let alone a specific part within that family.

In the case of the CD4013, if you are trying to minimize power then if you tie both the set and the reset HI, you should also tie the data input HI, otherwise you will be charging and discharging the charge storage node for the master section on each clock cycle. If you assert just the reset, then you should tie the data line LO to avoid the same pumping behavior.

Asserting both the set and reset inputs should not just be done blindly, since having both outputs HI can have unintended consequences. In the case where the outputs truly are not being used, this is immaterial. But sometimes a FF is used within a design and an option is to effectively remove it from the design (such as when the same circuit is used for different products and the differences are controlled by disabling certain parts of the circuit). If this is the case, then having both outputs of a FF be HI can cause problems because some parts of the circuit might see that state as being a 1 (those using the Q output) and others might see it as being a 0 (those using the /Q output). But this falls under the guidance given earlier that the level that you tie unused inputs to should reflect the functionality of the circuit.
I am using 74HC74 from Nexperia in my design
 

WBahn

Joined Mar 31, 2012
25,918
True, but if the FF is not being used you wouldn't want to route the clock to it as that will use power simply by charging/discharging the gates of the 6 or so internal clock buffers, irrespective of the other inputs. Unused inputs on a FF in use should be tied to either Vdd or Vss so as not to affect operation, ie for Set & Reset that would be ground, but if a whole FF isn't being used you'd tie all 4 inputs (including Clock) to whichever rail is easiest. The layout of a CD4013 makes Vss the logical choice, however tying some or all to Vdd is acceptable, it won't result in increased consumption.
True -- I forgot that that part has separate clock inputs for both DFFs. For so long I worked on designs in which a single global clock signal was hard routed via a minimal skew clock tree to all DFFs in that clock realm.
 

AnalogKid

Joined Aug 1, 2013
8,489
You can connect the S, R, D, and Clk inputs directly together, and tie the group to Vdd either directly or through a resistor. I would tie them to Vdd rather than GND because that is the disable (inactive) state for the S and R inputs.

ak
 
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