Hello everyone,

I'm trying to wrap my head around the concept of clock pulses, particularly in the context of SPI and I2C.

I understand that oscillators generate continuous square wave signals, but I'm a bit confused about clock pulses in the context of SPI and I2C.

I've come across terms like "set clock" "release clock." , "raising edge" and "failing edge"

How do these terms come into play with clock pulses, and what role do they serve in I2C clock signal?

 

a clock edge is just that , a rising or falling level.
depending upon the system, either a 0 to 1 transition or a 1 to 0 transition is the rising or falling edge,

terms like set clock and release clock sound like software terms, may be arduino related.

Sysytem like I2C or SP, the data is sent out on a clock edge, and grabbed at the receiver on a clock edge, not neciseraly the same edge,

https://en.wikipedia.org/wiki/I²C

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

 

Hello everyone,

I'm trying to wrap my head around the concept of clock pulses, particularly in the context of SPI and I2C.

I understand that oscillators generate continuous square wave signals, but I'm a bit confused about clock pulses in the context of SPI and I2C.

I've come across terms like "set clock" "release clock." , "raising edge" and "failing edge"

How do these terms come into play with clock pulses, and what role do they serve in I2C clock signal?

Are you familiar with D-type flip-flops such as the CD4013 or 74HC74?
If so, that is what is on the inputs - the clock signal is the clock of a D-type latch which latches in the data.

 

a clock edge is just that , a rising or falling level.
depending upon the system, either a 0 to 1 transition or a 1 to 0 transition is the rising or falling edge,

You're absolutely right! A clock edge refers to a transition in the signal level of a clock signal. it can be either a rising edge (low to high transition) or a falling edge (high to low transition).

The data is typically sent out or captured at specific clock edges.

I am interested to know about I2C clock signals. How does they work? Does master generates continue square wave signal? What does it means one clock signal is generated? Does it means voltage on SCL pin goes from high to low or low to high?

 

Hello everyone,

I'm trying to wrap my head around the concept of clock pulses, particularly in the context of SPI and I2C.

I understand that oscillators generate continuous square wave signals, but I'm a bit confused about clock pulses in the context of SPI and I2C.

I've come across terms like "set clock" "release clock." , "raising edge" and "failing edge"

How do these terms come into play with clock pulses, and what role do they serve in I2C clock signal?

While a clock signal is often a free-running square wave, the concept of a 'clock signal' in digital electronics is more general than that. Think of it as a signal whose purpose is to synchronize things so that they happen at the correct time.

In many communication protocols, the 'clock' is merely a digital signal that one or both parties have control over that is used to tell the other side that it is time to do something, such as capture the state of the signals on other lines.

 

I am interested to know about I2C clock signals. How does they work? Does master generates continue square wave signal? What does it means one clock signal is generated? Does it means voltage on SCL pin goes from high to low or low to high?

I2C is quite clever, because both the "master" and the "slave" can control SCL, either of them can drive it low, and a resistor pulls it high when neither of them is driving it.
Data is transferred on the rising edge of SCL, but if the slave is slow and needs more time, it can keep SCL low until it is ready.

 

In many communication protocols, the 'clock' is merely a digital signal that one or both parties have control over that is used to tell the other side that it is time to do something, such as capture the state of the signals on other lines.

I'm curious about the intricacies of transferring a single bit of data from an I2C master to a slave. Specifically, I want to grasp the exact sequence of events and, importantly, identify the precise clock edge at which master transfer bit and the slave receives this bit.

If you could provide a concise breakdown of the process or share insights on how the clock signal (SCL) influences this operation, it would greatly enhance my understanding. Visual aids or examples would be wonderful too.

 

Or, you could go look at the I2C protocol specification or any of the many, many reference guides and tutorials that are out there.

 

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

From the people that invented I2C.

 

Or, you could go look at the I2C protocol specification or any of the many, many reference guides and tutorials that are out there.

I stumbled upon this interesting image that illustrates the data transfer of the byte "1010 1010". It appears that data transitions on the SDA line are happening while the SCL is low. Additionally, SDA doesn't change state when the clock is high. Could someone help me decode this scenario?

 

It appears that data transitions on the SDA line are happening while the SCL is low. Additionally, SDA doesn't change state when the clock is high.

Correct for I2C data, SDA may change only when SCL is low. SDA must not change when SCL is high. That scenario is reserved for generating START and STOP conditions . Also, in the box you outlined in #10, you can see that the data bit value is read on the falling edge of SCL. That's the way I2C is designed.

The START and STOP conditions are generated by SDA changing when SCL is high. When SCL is high, SDA going 1 to 0 is a START condition, the beginning of an I2C message, and SDA going from 0 to 1 is a STOP condition indicating the end of message, the I2C bus is idle and another message may begin. Your picture does not show START and STOP.

 

Correct for I2C data, SDA may change only when SCL is low. SDA must not change when SCL is high. That scenario is reserved for generating START and STOP conditions . Also, in the box you outlined in #10, you can see that the data bit value is read on the falling edge of SCL. That's the way I2C is designed.

In I2C, either the master or the slave device can control the SCL line.

How does I2C ensure bidirectional control of the clock (SCL) line between the master and slave devices?

 

In I2C, either the master or the slave device can control the SCL line.

How does I2C ensure bidirectional control of the clock (SCL) line between the master and slave devices?

"The possibility of connecting more than one microcontroller to the I2C-bus means that more than one controller could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event, an arbitration procedure has been developed. This procedure relies on the wired-AND connection of all I2C interfaces to the I 2C-bus. If two or more controllers try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ loses the arbitration. "

This is straight from the guide that JohnInTX tried to get you to take a look at.

You might want to take a look at it. It's only 64 pages long. Read it and then ask questions about things that aren't clear, pointing to the sections where your confusion lies.

 

View attachment 300248

I stumbled upon this interesting image that illustrates the data transfer of the byte "1010 1010". It appears that data transitions on the SDA line are happening while the SCL is low. Additionally, SDA doesn't change state when the clock is high. Could someone help me decode this scenario?

Hi,

The general idea of a clock is that signal tells the receiver WHEN to sample the data. There is often some noise and rise time of the data line so the receiver has to be told when the data signal is valid. When the data is valid, the clock pulses so that the receiver can sample the data line and record the signal level. After several of these occurrences, the receiver then has one complete byte or whatever it is looking for.
In your image you can see that the data line goes high significantly sooner than the clock pulse, and similarly, if the data is a 'low' it goes low sooner than the clock pulse. When the receiver gets the clock pulse it takes in the state of the data line and stores that, then waits for the next clock.

This kind of communication can be either one way or the receiver and transmitter can switch places so they can talk back and forth. The most common is one way, where you have what they used to call the 'master' and one or more 'slaves'. Those terms are being deprecated though for obvious reasons.

 

I'm curious about the intricacies of transferring a single bit of data from an I2C master to a slave. Specifically, I want to grasp the exact sequence of events and, importantly, identify the precise clock edge at which master transfer bit and the slave receives this bit.

If you could provide a concise breakdown of the process or share insights on how the clock signal (SCL) influences this operation, it would greatly enhance my understanding. Visual aids or examples would be wonderful too.

The exact sequence of i2c is fully covered in the wiki link and the associated i2c spec it links to.
Also try this for a background
https://embedded-lab.com/blog/lab-14-inter-integrated-circuit-i2c-communication/

 

Hi,
In your image you can see that the data line goes high significantly sooner than the clock pulse, and similarly, if the data is a 'low' it goes low sooner than the clock pulse. When the receiver gets the clock pulse it takes in the state of the data line and stores that, then waits for the next clock.

From what I understand:

SCL Pulled Low by the Master: The master device initiates the clock pulses by actively driving the SCL line low. This means the master briefly connects the SCL line to ground (GND) to create a low logic level (Logic 0) on the line.

Pull-Up Resistor Pulls SCL High: When the master releases the SCL line, the pull-up resistor connected to the SCL line ensures that the line is pulled back to a high logic level (Logic 1). The pull-up resistor provides a path for current to flow from the supply voltage (Vcc) to the SCL line.

Creating Clock Pulses: The process of the master pulling the SCL line low and then the pull-up resistor pulling it high creates a clock pulse. Each clock pulse indicates a timing interval,

Does master write bit at leading edge and slave read bit at falling edge of clock signal ?

 

From what I understand:

SCL Pulled Low by the Master: The master device initiates the clock pulses by actively driving the SCL line low. This means the master briefly connects the SCL line to ground (GND) to create a low logic level (Logic 0) on the line.

Pull-Up Resistor Pulls SCL High: When the master releases the SCL line, the pull-up resistor connected to the SCL line ensures that the line is pulled back to a high logic level (Logic 1). The pull-up resistor provides a path for current to flow from the supply voltage (Vcc) to the SCL line.

Creating Clock Pulses: The process of the master pulling the SCL line low and then the pull-up resistor pulling it high creates a clock pulse. Each clock pulse indicates a timing interval,

Does master write bit at leading edge and slave read bit at falling edge of clock signal ?

For i2c,
We have a start coditio, a stop condition, and data transfer
All are as per the spec, and are dependent upon the edges and levels of sda and scl.

 

I wanted to share my understanding of the data transmission process for I2C . I'm hoping to get your insights and corrections to ensure that I have a clear grasp of the concept. I believe this could be beneficial for others who are also exploring I2C. So, without further ado, here are the steps as I understand them:

I2C Data Transmission : Address and Data

Step 1: Start Condition
To start communication on the I2C bus, we start with a Start Condition:

• Set the SDA line to a logic low level.
• Keep the SCL line high.

Step 2: Address and Data Transmission
Next, we transmit the Slave Address and indicate whether we want to Read or Write data:

• Transmit the Slave Address (7 bits), which for this example is 1001010.
• Include the Read/Write (R/W) Bit, where 0 signifies a Write operation.
• Await an Acknowledgment (ACK) from the addressed slave to confirm its presence.

Understanding the Data Validity and Change:

• Data is considered valid when the SCL line is high.
• Data changes should occur when the SCL line is low.
• Stable data is indicated by the rising edge of the SCL signal.

Step 3 : 8-Bit Transfer for Address : example is 1001010.

For each bit of the 7-bit Slave Address:

• When the SCL line is low, set the SDA line according to the bit being transmitted.
• Bit 1 (MSB): Set SDA high while SCL is low (Transmit 1).
• Bit 2: Set SDA low while SCL is low (Transmit 0).
• Bit 3: Set SDA low while SCL is low (Transmit 0).
• Bit 4: Set SDA high while SCL is low (Transmit 1).
• Bit 5: Set SDA low while SCL is low (Transmit 0).
• Bit 6: Set SDA high while SCL is low (Transmit 1).
• Bit 7: Set SDA low while SCL is low (Transmit 0).

Step 4: Acknowledge (ACK) and Not Acknowledge (NACK)
After sending the Slave Address, await an Acknowledgment (ACK) or Not Acknowledge (NACK):

• The slave device sends an ACK if the address was successfully received.

Step 5: 8-Bit Transfer for Data : For example 10101010

• For each bit sent, master sets SDA line while SCL is low
• Bit 1 (MSB): Set SDA to high while SCL is low (Transmit 1)
• Bit 2: Set SDA to low while SCL is low (Transmit 0)
• Bit 3: Set SDA to high while SCL is low (Transmit 1)
• Bit 4: Set SDA to low while SCL is low (Transmit 0)
• Bit 5: Set SDA to high while SCL is low (Transmit 1)
• Bit 6: Set SDA to low while SCL is low (Transmit 0)
• Bit 7: Set SDA to high while SCL is low (Transmit 1)
• Bit 8 (LSB): Set SDA to low while SCL is low (Transmit 0)
• SDA state changes according to the data while SCL is low
• SCL transitions high to signal data readiness

Step 7: Acknowledge (ACK) and Not Acknowledge (NACK)
Again, await an Acknowledgment (ACK) or Not Acknowledge (NACK):

• The slave device sends an ACK if the data was successfully received.

Step 8: Stop Condition
To stop the transmission, we send a Stop Condition:

• Set the SDA line high while SCL is high.

 

Do you understand simpler protocols like SPI? The complexity of I2C would be easier to understand if you knew a simpler one and it’s limitations. The complexity comes from trying to overcome the limitations.

 

Do you understand simpler protocols like SPI? The complexity of I2C would be easier to understand if you knew a simpler one and it’s limitations. The complexity comes from trying to overcome the limitations.

I understand SPI protocol, the clock in the SPI protocol acts as a timing reference, allowing the master and slave devices to communicate effectively by ensuring that data is transmitted and received at the correct moments based on the chosen clock polarity and phase settings. Each clock pulse represents a bit of data being transferred. The master generates a clock pulse for every bit of data it wants to send or receive.