Can anybody help me design a clock fail detection cicuits without using delay lines.
I came across the attached circuit which can detect the clock failure of a high frequency clock used as clock1 with the help of a good low frequency clock named clock2.
My doubt is whether i can detect the failure of the low frequency clock with the help of a good high frequency clock?
I have attached waveform of the below circuit and my requirement is the reverse.
Pls help

 

are you constrained in any manner on your design?

If you are not, search for Application Note 170 from Phillips Semiconductors. The 555 timer can be a missing pulse detector.

 

I am planning to use this along with adpll. So my input frequency(clock1) can vary between 61khz to 43Mhz and clock2 is 250mhz.
Also i dont want to use a frequency divider to divide the 250mhz because to match with my input i may need large dividers.

 

are you constrained in any manner on your design?

If you are not, search for Application Note 170 from Phillips Semiconductors. The 555 timer can be a missing pulse detector.

I am planning to use this along with adpll. So my input frequency(clock1) can vary between 61khz to 43Mhz and clock2 is 250mhz.
Also i dont want to use a frequency divider to divide the 250mhz because to match with my input i may need large dividers. I need to code the design in verilog hdl

 

61 kHz through 43 MHz and clock 2 at 250 milliHertz?

 

61 kHz through 43 MHz and clock 2 at 250 milliHertz?

61Khz to 43Mhz and 250Mhz

 

If your planning on using TTL devices, you know 41 MHz is outside their operating range ... and so is 250 MHz.

 

I want to code such a circuit in verilog hdl and simulate it. I have attached a similar circuit in thread 1