Hi,
i'm designing and realizing on prototypal board the class d amplifier in figure below



the problem is that the Infineon MOSFETS become too hot beyond the calculations that I made, also without load and with lower voltage than i need. Also they present 100ns of miller plateau at which the measured current on high side mosfet drain is of any amperes.

I test many mosfets and they all have the same problem maybe less pronounced.

The only one that doesn't have that kind of dissipation issue is International Rectifier mosfet in figure.

What do you think? Is it a bad driving or parasitic components of other mosfets?

I'm looking for a mosfet with lower Rds in order to increase output power...
Could you help me?
Thanks

 

What is the switching rate? Read my post in this forum thread.

 

The switching rate is 50KHz.

 

The switching rate is 50KHz.

What sort of heatsinking for the FETs do you have?

 

A D2pack heatsink Rth=15°C/W but now i'm doing test without it mounted

 

How much deadtime do you have between the switching of the upper MOSFET and the lower MOSFET?

 

How much deadtime do you have between the switching of the upper MOSFET and the lower MOSFET?

i tried different dead times from 20ns to 100ns but nothing changes

 

i tried different dead times from 20ns to 100ns but nothing changes

How do you generate the dead (non-overlap) time?

 

pwm signals are generated by fpga and are connect to adum input pins

 

I'm trying to determine what the two signals look like that are driving the top and bottom MOSFETs in the bridge.
Where does the deadtime occur?

 

Could you explain me better?

 

Okay. I'm trying to determine if the deadtime delays are being done correctly, i.e. does the top transistor always turn OFF before the bottom transistor turns ON, and does the bottom transistor always turn OFF before the top transistor turns ON.

 

Okay. I'm try to determine if the deadtime delays are being done correctly, i.e. does the top transistor always turn OFF before the bottom transistor turns ON, and does the bottom transistor always turn OFF before the top transistor turns ON.

Especially considering the FET turn off delay as shown in the sim I linked to...