Mr. Chips, I thought that might be the case - bushrat said he is using MC74HC4020N. It is vastly faster than the 4000 series part.

Is 4000 series popular with experimenters? I have a certain fondness for it, mostly because of the wide supply voltage range. It is interesting how many of the parts have been translated into newer faster CMOS families. The 4040 counter exists in AC and will run at 140 MHz!

 

Clock to Q1 is 260 ns and clock to Q14 is 1820 ns. This tells me that the "ripple" in this ripple counter is significant. The Reset pulse is initiated when Q5 goes high after the other four high order bits already are 1's, and terminated by Q14 when it goes low.

The actual reset signal doesn't start until the low to high state transition of Q5 propagates through three levels of gating. U3D is the One Gate to Rule Them All.

 

MrChips stated in post #14 that he breadboarded the circuit and had no problems. The only thing we can do is wait for an update from Bushrat to see if he miswired something, has a bad part or both.
SG

 

A
Question here is if the register bits all reset at once or in some sequence or on a sliding scale. But Id rather say they do at once. There could be buffered and unbuffered variants.)

That is really the hook in all such circuits. With a monolithic counter is is reasonably reasonable to expect all of the flip flops to clear within a very small time differential. If the counter requires multiple packages, it becomes much less reasonable to expect them all to have the same delay. If you get into really high speed logic, delays through interconnects can become significant - I would argue you're something of a fool if you try to generate async clear for such.

There are things you can do using RS flip flops - set the flop on assertion of the clear signal from the gating and clear it with the clock (e.g. if the counter clocks on rising edge, use the LOW time of the clock to clear the flip flop). There are many useful things that can be done with using opposite edges or states of clocks, but you can also make a mess of setup time requirements if you aren't careful.

 

Ok, so here is my circuit, omitting CD4017 for now.
Crystal on top, 7474 below, 4020 below that, and 7408 on right side.



On last gate (MR signal on 4020), I get a very tiny pulse.

 

Look at the inputs to that last AND gate in your reset logic and see if one of those inputs is short. Then walk it back.

Or, just look at each of the 4020 outputs you are ANDing together and see if one of them is short while the others are long (or stay HI).

 

Decoupling capacitors required!
All conductors have inductance. With fast current transitions, as happen during the edges of CMOS signals, the inductance causes voltage dips and spikes. Decoupling capacitors provide local charge reservoirs.
Add a ceramic capacitor of around 100 nF (10 nF to 1 µF OK) between V+ and ground at each IC. Keep the leads as short as possible to minimize the inductance between the cap and the IC. It is generally good practice to add a "bulk" capacitor of a few microfarads somewhere near the power entry to be board. Tantalum is "best"-ish, but an aluminum electrolytic can be OK. 10 to 100 µF range is typical.

The waveform looks pretty much exactly as I would expect it to. The width is just as expected with an HC counter. The amplitude is on the low side because the capacitance of the probe represents a significant load for the output. The amplitude will likely improve when decoupling caps are added.

 

Also, when probing, use the shortest ground lead you have for your scope probe and connect it very close to the ground pin of the counter.

Be sure the compensation cap in the probe is properly adjusted.

 

Mr. Chips, I thought that might be the case - bushrat said he is using MC74HC4020N. It is vastly faster than the 4000 series part.

Is 4000 series popular with experimenters? I have a certain fondness for it, mostly because of the wide supply voltage range. It is interesting how many of the parts have been translated into newer faster CMOS families. The 4040 counter exists in AC and will run at 140 MHz!

bushrat is using 74HC4020 which is much faster - 20 times faster.
Propagation delay from MR to Qn is 19ns.

 

1uF caps added next to each Vcc pin and ground.
Q1 is 125kHz
Q4 is 15.63 kHz
Q5 is 7.812 kHz
After that I an noticing pulse width changing,
Picture is showing the changes in pulse width as double exposure.

I also used short ground lead for o-scope, no change in reset signal.

 

You could read the CMOS cookbook this guy has been there and built circuits of all kinds, you can find a lot of useful information how to get along. Back then they didnt have these hitech oscilloscopes on the market. Breadboards were expensive and local shops didnt have them.

So it was soldered, all you were able to use was LEDs, if it didnt work, you had to think it over again, try a different approach.

Now you could simulate it...have the high tech gear to see the actual waveforms. IC testers even.
The worst thing you can get is ICs partially latching up, they still work when you test them but give you improper waveforms leaks and stuff.

Also I sometimes found, for some circuit, when I had same IC by different manufacturer, some the LED would be bright, some rather dull, others erratic or just not working. There is specs in the datasheet and there is reality...

Of course when you dont put the capacitors, you have a lot of information still to consider, its a no-no, you always need them for digital ICs.
Wire length, you dont get much effect at less than 30cm, so if it is 3cm or 4cm doesnt make a difference.
Basically without the capacitors, the circuit can not work properly, i have seen controllers working without any then suddenly reset or hang up.
Modern aluminium kinds are normally fine but older kinds could be problematic, foils are not effective, usually ceramic is the kind thats most suitable. 100nF is actually fairly short, you could use 0.47uF

 

1uF caps added next to each Vcc pin and ground.

Are those electrolytic?
Best is 0.1μF ceramics.

 

1uF caps added next to each Vcc pin and ground.
Q1 is 125kHz
Q4 is 15.63 kHz
Q5 is 7.812 kHz
After that I an noticing pulse width changing,
Picture is showing the changes in pulse width as double exposure.
View attachment 148196
I also used short ground lead for o-scope, no change in reset signal.

Use the MR signal as your trigger. You want to examine the pulse widths of the pulses that are causing the reset event.

 

The actual reset signal doesn't start until the low to high state transition of Q5 propagates through three levels of gating. U3D is the One Gate to Rule Them All.

Not for the leading edge of the reset pulse. At that time, Q14 is high both before and after the Q5 low-high transition. Q14 initiates *only* the trailing edge of the reset pulse.

ak

 

Question here is if the register bits all reset at once or in some sequence or on a sliding scale.

The CD4020 has a parallel reset. The internal reset signal goes to all output flipflops with no intentional delays among the signals.

ak

 

Not for the leading edge of the reset pulse. At that time, Q14 is high both before and after the Q5 low-high transition. Q14 initiates *only* the trailing edge of the reset pulse.

ak

The state transition that leads to generation of the reset pulse is the Q5 low to high transition. Not until that has propagated through three levels of gate does the actual reset pulse does not begin.

• Q5 goes high.
• One gate delay later U3A output goes high.
• One gate delay later U3C output goes high.
• One gate delay later U3D output, the actual reset signal, goes high.

If the gating were done with a single gate, then there would be a single gate delay to initiation of MR with Q5 went HIGH. MR would end one gate delay after the first of the gated outputs went LOW.
[Edit:] If the Q5 and Q14 inputs to the gates were swapped, then MR would be asserted a single gate delay after the low to high transition of Q5 and de-asserted one delay after the opposite transition on Q5.

 

And then there is:

All unused INPUTS for the 4000 family have to be tied to Vcc or ground. The chips oscillate and get hot if not. I would need to check the other families mentioned.

 

 

KISS - ALL CMOS inputs need to be trussed up or tied down, with very rare exceptions where the input is something quite unusual (typically 3-state - it does three distinctly different things depending on whether it is HIGH, LOW or open; something internal to the chip establishes the level when the pin is left unconnected). TTL inputs will float at logic high (since there is a need to sink current from the inputs for logic low), but it is still good practice to tie unused inputs. With LS those that need to be HIGH can be tied to the Vcc. With standard TTL they should be tied through (iirc) a 1k resistor, which can be shared by numerous inputs. Under normal circumstances std TTL inputs could be tied to the rail, but the spec for absolute max input voltage for std TTL is lower than the spec for abs max Vcc, whereas for LS it is the same.

~~~
All this worry about async clear could be avoided by simply using an INTUITIVE-WHEN gate to drive the reset. I guess the requirement for ±150V supplies and 3 low voltage supplies makes them unpopular.

 

74HC4020 is too fast. The reset pulse is about 20ns.

You need to stretch the reset signal from 7408 U3D to MR as AK posted in post #12.
Connect 1kΩ resistor from 7408 U3D output to MR. Connect 100pF from MR to GND. This will stretch out the MR signal to about 200ns.

There is a glitch in there I have yet to identify as warned by WBahn.