If you are going to use a stretcher, Dick's circuit at #38 is better because of the diode. A diode can also be added to AKs circuit.
LS TTL is barely able to meet the logic 1 requirement for HC. Typical output HIGH for LS is about 3.4 V, which is sufficient. The minimum guaranteed spec is 2.5 V, which right at the ragged edge (both when sourcing 400 µA). The minimum input HIGH spec for HC is going to be a little above 2.4 volts. When the diode drop is figured in there is no margin to negative margin. The solution to this is to add a pullup resistor on the output of the LS gate. Since you want to charge the stretcher capacitor as fast as possible, a resistor of around 2.2k would be suitable. You could go as low as 1k and without "overloading" the gate output, but it is a power waster almost 100% of the time.
With CMOS you can set the pulldown resistor in Dick's circuit to an almost arbitrarily high value since the input current of CMOS is just leakage current, spec'd at a max of ±1 µA at 85°C. The pulldown resistor alone sets the discharge time of the capacitor. During the discharge, particularly, the MR signal will be at a "bad" logic level.
Once again, depending on how these circuits are implemented you will trade a short but clean reset for a longer but sloppy one unless cleaned up with a schmitt trigger. Sloppy is likely just fine in this instance. When scoping such circuits, compare the output of the gate with the input at MR.
LS TTL is barely able to meet the logic 1 requirement for HC. Typical output HIGH for LS is about 3.4 V, which is sufficient. The minimum guaranteed spec is 2.5 V, which right at the ragged edge (both when sourcing 400 µA). The minimum input HIGH spec for HC is going to be a little above 2.4 volts. When the diode drop is figured in there is no margin to negative margin. The solution to this is to add a pullup resistor on the output of the LS gate. Since you want to charge the stretcher capacitor as fast as possible, a resistor of around 2.2k would be suitable. You could go as low as 1k and without "overloading" the gate output, but it is a power waster almost 100% of the time.
With CMOS you can set the pulldown resistor in Dick's circuit to an almost arbitrarily high value since the input current of CMOS is just leakage current, spec'd at a max of ±1 µA at 85°C. The pulldown resistor alone sets the discharge time of the capacitor. During the discharge, particularly, the MR signal will be at a "bad" logic level.
Once again, depending on how these circuits are implemented you will trade a short but clean reset for a longer but sloppy one unless cleaned up with a schmitt trigger. Sloppy is likely just fine in this instance. When scoping such circuits, compare the output of the gate with the input at MR.