CD4020 and gates problem

Discussion in 'Digital Circuit Design' started by bushrat, Mar 11, 2018.

  1. ebp

    Well-Known Member

    Feb 8, 2018
    1,401
    464
    If you are going to use a stretcher, Dick's circuit at #38 is better because of the diode. A diode can also be added to AKs circuit.

    LS TTL is barely able to meet the logic 1 requirement for HC. Typical output HIGH for LS is about 3.4 V, which is sufficient. The minimum guaranteed spec is 2.5 V, which right at the ragged edge (both when sourcing 400 µA). The minimum input HIGH spec for HC is going to be a little above 2.4 volts. When the diode drop is figured in there is no margin to negative margin. The solution to this is to add a pullup resistor on the output of the LS gate. Since you want to charge the stretcher capacitor as fast as possible, a resistor of around 2.2k would be suitable. You could go as low as 1k and without "overloading" the gate output, but it is a power waster almost 100% of the time.

    With CMOS you can set the pulldown resistor in Dick's circuit to an almost arbitrarily high value since the input current of CMOS is just leakage current, spec'd at a max of ±1 µA at 85°C. The pulldown resistor alone sets the discharge time of the capacitor. During the discharge, particularly, the MR signal will be at a "bad" logic level.

    Once again, depending on how these circuits are implemented you will trade a short but clean reset for a longer but sloppy one unless cleaned up with a schmitt trigger. Sloppy is likely just fine in this instance. When scoping such circuits, compare the output of the gate with the input at MR.
     
    bushrat likes this.
  2. AnalogKid

    AAC Fanatic!

    Aug 1, 2013
    6,944
    1,968
    What I suggested in #12 delays both the onset and release of the Reset input (both edges of the reset pulse). The delayed onset is what is needed; the delayed release is a consequence of the circuit.

    If something about the overall circuit makes the timing of the reset is more critical (not tolerant of the delay), then the circuit DC posted in #38 is better. It still stretches the reset pulse enough to eliminate any speed issues, but it has minimal delay of the reset leading edge (the part that does the resetting), and delays the trailing edge to make sure everyone gets the message. The downside is that it can pass through glitches in the reset signal caused by differential delays in the ripple counter outputs that drive the gating. The delay circuit in #12 also is a lowpass filter that attenuates that kind of noise.

    ak
     
    bushrat likes this.
  3. MrChips

    Moderator

    Oct 2, 2009
    16,461
    5,056
    Change the way you create your 5-input AND gate. Wire the inputs like this to avoid glitches.

    5-input AND gate.jpg
     
    bushrat likes this.
  4. BobaMosfet

    Senior Member

    Jul 1, 2009
    322
    68
    There is also a propogation delay for each gate, which will shift the waveform each time, I believe. Something to be aware of, if not already looked at.
     
    bushrat likes this.
  5. ebp

    Well-Known Member

    Feb 8, 2018
    1,401
    464
    Someone convince me there is a possibility of a glitch in the MR output on the up-count. There may be, but I don't immediately see it.

    We are looking only for HIGH states of the gated stages to generate MR.
    Stage n of the counter goes HIGH one flip-flop delay time after ALL previous stages have gone LOW e.g. 0001 1111 > 0010 0000, so by the time an "arming" stage has gone HIGH, all stages below it are well established at LOW, at least internally.
    0001 1111
    0001 1110
    0001 1100
    0001 1000
    0001 0000
    0000 0000
    0010 0000​

    There is a critical requirement here: the propagation delay through the whole counter to the highest stage of interest should be shorter than the clock period, otherwise a low order stage can be changing on clock n while higher stages are still waiting for the effect of clock n-1 or even earlier to arrive. Generating a reset from gated outputs in the latter case is doomed to failure. Doooooomed, I tells ya.

    The 4020, either in original 4000 series or HC, is specified for a max clock rate of about 1/[stage-to-stage propagation delay], which is reasonable given that a flip-flop requires feedback from its own output to its input to set up for the next state. You could get pretty close to have 14 clocks "in the pipe."
     
    bushrat likes this.
  6. WBahn

    Moderator

    Mar 31, 2012
    22,752
    6,777
    It's not so much a question of whether there actually IS a possibility for a glitch, as that if you (the designer) are going to enter the land of asynchronous logic, you have to ASSUME there is the possibility of a glitch UNLESS you go through ALL of the analysis to PROVE that there isn't.

    You ALSO have to assume that, upon asserting the MR signal, that the internal FFs are going to reset in a random order, with the first doing so at the shortest possible time and the last doing so at the longest possible time, and that the external MR pulse generation circuit is going to response accordingly, thus setting up a race between the fastest FF to reset causing the MR signal to go away before the slowest FF can respond to it. So it is then YOUR responsibility to determine what the shortest possible MR pulse might be and compare that to the shortest acceptable MR pulse.

    These are the kinds of things that almost no one that dabbles in this kind of logic bothers to consider.
     
    bushrat and ericgibbs like this.
  7. MrChips

    Moderator

    Oct 2, 2009
    16,461
    5,056
    I do not have a 74HC4020 but I do have a 74HC4040 for testing.

    Here is what I am seeing that results in a glitch.

    Suppose you have one output going HIGH into the last AND gate (U3D).
    Suppose you have the output of another stage going LOW but has to propagate through two AND gates. Thus, the LOW-to-HIGH signal is early (actually, on time) but the HIGH-to-LOW signal is delayed. You get a wispy glitch at the output of the AND gate that can cause trouble. This I can actually observe on the oscilloscope.
     
    bushrat likes this.
  8. ebp

    Well-Known Member

    Feb 8, 2018
    1,401
    464
    WBahn I totally agree about the risks in the general case. The analysis is tedious and I would be disinclined to trust simple simulation without knowing the details of the models. It is the sort of thing good simulation is good for, but I don't know that any of the popular free simulators are up to the task, and even if they are if users know how to give them correct marching orders. This particular case has been looked at quite closely and I believe it actually will work as desired while meeting requirements. However, all it would take is for one specification to be a bit different and it would cross from workable to not workable.

    I raised the issue of the glitch specifically because we now seem to have an unsupported notion that this particular circuit will generate a glitch and/or a pulse stretcher is required. Putting in an RC pulse eater/stretcher to avoid doing the analysis is just as bad as failure to do the analysis, in my opinion.

    RC circuits stuffed into digital circuitry are much like async logic. They can work, but they must be considered carefully. Pulse stretchers and glitch eaters are among the circuits that present high risk because, of necessity, they force signal levels into the "forbidden" zone.
     
    bushrat likes this.
  9. MrChips

    Moderator

    Oct 2, 2009
    16,461
    5,056
    The purpose of the RC is not to remove glitches. Its purpose is to slow down the arrival of the encoded 5-input AND output to the MR input. This will stretch out the length of the MR pulse.

    I can observe the glitch with or without the RC components installed.
     
    bushrat likes this.
  10. RichardO

    Senior Member

    May 4, 2013
    2,207
    853
    I would argue that it is required to both remove the narrow glitches and stretch the reset pulse. The glitches that occur at counts before the decoded state can cause a (partial) premature reset. Too short a reset pulse might not reset all of the flip-flops in the counter.
     
    bushrat likes this.
  11. ebp

    Well-Known Member

    Feb 8, 2018
    1,401
    464
    The circuit without a diode is NOT a reasonable pulse stretcher. It has now been proposed as a pulse stretcher and a glitch eater.

    It makes the width of the pulse at the output of the final gate wider, but that benefits nothing by itself. What arrives at the MR input is a signal that slops its way slowly up to about half of Vdd where it is interpreted as logic 1, even though it is a bad level and hence very subject to noise taking it back down to zero. As soon as the first flip flop is cleared and that propagates to the output of the final gate, discharge of the cap begins. Chances are the MR signal never arrives at a good clean logic 1 level.

    There is zero reason to delay the arrival of the signal from the final gate to MR if you aren't trying to eat glitches. What you want is for it to arrive as soon as possible but go away a bit later than it normally would. If you add a diode to the RC circuit this can be accomplished, but it is still a bad circuit without a schmitt trigger to clean it up (or an input that already has hysteresis).
     
    bushrat likes this.
  12. ebp

    Well-Known Member

    Feb 8, 2018
    1,401
    464
    I would argue that if you are generating glitches due entirely to bad gating your design is bad. If you are attempting to stretch pulses with an RC network without due attention to generating a clean signal with proper rise and fall times and proper logic levels your design is bad.
     
    bushrat likes this.
  13. MrChips

    Moderator

    Oct 2, 2009
    16,461
    5,056
    Hey, I'm not arguing with you. We are just trying to figure out why the TS's circuit is not working.
     
    bushrat likes this.
  14. ebp

    Well-Known Member

    Feb 8, 2018
    1,401
    464
    Have we in fact established that it does not work? Until proper decoupling is in place, all bets are off. The last reset pulse he showed will meet the minimum reset width for the HC part, though not with a lot of margin. It will meet the typical with lots of margin, but relying on that isn't wise either. It is hard to assess it accurately due to oscilloscope issues - unfortunately it is something for which faster scope with a 500 ohm or active probe would be helpful. Good thing it isn't an AC counter.

    bushrat - what is the specified tip capacitance for your scope probe?
     
    bushrat likes this.
  15. ebp

    Well-Known Member

    Feb 8, 2018
    1,401
    464
    I've had enough electronics for today (actually, I'd had enough for a lifetime a couple of years ago) but ...

    If glitches arise at gate outputs and "flat" gating isn't possible, could the glitches be put down by assuring that no gate has its inputs connected to adjacent stages of the counter?
     
    bushrat likes this.
  16. bushrat

    Thread Starter Member

    Nov 29, 2014
    209
    57
    All pins have pulses, square wave, different frequencies as predicted.

    1 uF Tantalum
    .
    IMG_20180313_170448457.jpg
    This streched my signal to 200 nS. Not sure how this will affect my "seconds" pulse in my final clock. Thank You for suggestion.

    All inputs are used one way or other, not floating anymore.. learned that lesson not to long ago.
     
  17. WBahn

    Moderator

    Mar 31, 2012
    22,752
    6,777
    I'm not looking for whether there are pulses or what their frequencies are. I am interested in the ONE pulse that occurs when the MR pulse is generated. Whether pulses occur at other times is completely irrelevant to the question of what is happening during the reset event. For that you need to know that you are looking at the one, specific pulse in each pulse train. That is why you want to trigger on the MR pulse. Depending on your scope's abilities, you might only see the falling edges of the pulses (since the rising edges occur before the MR rising edge), but that's fine because it's the falling edges we care about.
     
    bushrat likes this.
  18. bushrat

    Thread Starter Member

    Nov 29, 2014
    209
    57
    The only instance of rising pule I wound is on Pin 5 (Q5),
    Yellow is MR, Blue is Q5
    IMG_20180313_190230697.jpg

    Q5 is an input to AND gate,
     
    Last edited: Mar 13, 2018
  19. WBahn

    Moderator

    Mar 31, 2012
    22,752
    6,777
    This might indicate that Q5 is the last one to go HI. Not sure that that makes sense. I'd have to look at the internals to see.

    But, again, we don't care about the rising edges. It's the falling edges we care about. Do ALL of them fall?
     
  20. ebp

    Well-Known Member

    Feb 8, 2018
    1,401
    464
    Oh, what the heck ... not doing anything useful.

    The waveform at 58 is exactly as expected. The output of the gate goes high about 35-40 ns (three gate delays) after Q5 goes high - Q5 going high is when reset should be asserted.
    The "stretcher" greatly delays assertion of MR as evidenced by the fact that Q5 starts on its way low right around the 150 ns mark (i.e post-trigger). MR probably was actually taken as HIGH about the 130-135 ns mark - this based on the datasheet spec for the propagation delay from from MR to outputs. The "stretcher" merely delayed assertion of reset by about 130 ns. At this point, we know nothing of any actual stretching nor do we know that MR actually looks like.

    It is interesting to see the slew rate of the HS signal is greater than that of the LS.

    [EDIT] If reset is working properly, all 5 of the signals gated to generate it should be going LOW at within a few nanoseconds of the time that Q5 goes LOW.
     
Loading...