This might indicate that Q5 is the last one to go HI. Not sure that that makes sense. I'd have to look at the internals to see.

But, again, we don't care about the rising edges. It's the falling edges we care about. Do ALL of them fall?

at 500 nS/Div, a lot of pins look same.
Yellow is MR, Blue is pin signal:

Q1, Q4, Q9, Q10, Q11, Q14 look like pic above


Q6, Q7, Q8, Q12, Q13 are flat.


Q5 is the only one different, see above.

 

If you crank up the horizontal deflection you should be seeing a sequence of distinct events at intervals of around 15-20 ns

clock goes high
Q1 goes low
Q2 goes low
Q3 goes low
Q4 goes low
Q5 goes high
output of gate goes high (scope triggers)​

At 500 ns per div they will all look the the same

[EDIT - added Q2 and Q3 which aren't pinned out, & clock]

 

at 500 nS/Div, a lot of pins look same.
Yellow is MR, Blue is pin signal:

Q1, Q4, Q9, Q10, Q11, Q14 look like pic above


Q6, Q7, Q8, Q12, Q13 are flat.


Q5 is the only one different, see above.

Going back and looking at the original schematic, it makes sense that Q5 is the one that triggers the reset.

All of the others are resetting to zero.

So I'm at a loss as to what the problem is. You said that it keeps counting. But all of the outputs reset to zero when it reaches the count value you are looking for and then starts counting again from zero. That's what the schematic says it should be doing.

So what, exactly, is the problem?

A capture of the simulation and the scope showing the difference in behavior would go a long way.

 

What is the frequency at the output of the final gate?

Note the small glitch in the blue trace near the trailing edge of the reset pulse in the centre photo. That is a Disturbance in The Force caused by several outputs of the counter changing state at one time. This results in a fairly large supply current spike and is exactly the sort of thing decoupling caps are for. Some of it will also be contributed by "ground bounce."

 

I have determined that the RC components are not required.

The deciding signal is the least significant bit, which in this case is Q5. When Q5 goes from LOW-to-HIGH the MR feedback pulse is generated.

During counting, all outputs after Q5 change state on the HIGH-to-LOW transition of Q5. If Q5 is delayed because of 7408 propagation delays, then glitches will occur at the output of the AND gate.

Q5 should be on the input of the final AND gate, i.e. at U3D, to avoid generating glitches.

None of this explains why the TS's circuit continues to count after the terminal count is reached.

 

None of this explains why the TS's circuit continues to count after the terminal count is reached.

Based on his description of the screen shots of his scope, it doesn't.

 

TS should clock the 4017 Johnson counter with output taken from Q14.

 

Presumably bushrat can use his scope to directly measure the frequency at Q14. If the frequency is correct, the reset works, though it does not confirm adequate margin on the reset signal or the absence of glitches that could be troublesome.

I'd still like to see the waveform at MR with the "stretcher" in place.

 

at 500 nS/Div, a lot of pins look same.
Yellow is MR, Blue is pin signal:
View attachment 148255

That is not looking good. It is taking a whopping 100ns from MR to Q5 Low, while it should only be around 35 ns.

Is Q13 still at 30.49 Hz.,? That means it is 250kHz / 8192, and not getting reset. Whereas it should be at 250kHz / 10000 = 25 Hz., as it has only one pulse in the 10000 count cycle.

MR Pulse stretching should not affect final 'seconds' as your basic clock is 4 uS, way above the pulse and propagation delays!
Most likely, VIH min requirement of MR is 3.5V, is not being met. Scope plot gives it as 3.68V pp, but it has overshoot and undershoots. Better is to replace other family ICs with 74HC family. Can try pulling it up with a 1K resistor to check.
Q13 freq. can be measured to confirm.

PS : Please see next message for the scope plot.

 

The only instance of rising pule I wound is on Pin 5 (Q5),
Yellow is MR, Blue is Q5
View attachment 148253

Q5 is an input to AND gate,

I meant to attach this waveform!

 

RamaD, it is working and all has been discussed. There is a delay circuit on MR, though I'm not certain exactly which version that has been suggested.

 

Thanks for clarifying. The three waveforms in which various Q outputs with MR suggested it was working. But then, this 30.49Hz., Oh, that must have been earlier. Sorry, I was going back and forth and did not correctly sequenced it.

 

So what, exactly, is the problem?

The original problem was that the MR signal was too quick, 20 nS, and it would not be long enough to reset anything. RC circuit solved that. Thank you.

Second problem was that (I can only assume) the traces on my protoboard were not in best shape and there was connection issue from U3D to MR pin. Signal was being send, but pin would not detect it. Once I re-assembled circuit again, it worked.

I Apologize for late delay, but everything is working now as it should. Thank you to everyone.

 

I am still unconvinced that the RC circuit, if just an R and a C without a diode, helps more than a tiny amount.
Could you post a scope photo of the actual reset signal at the input of the counter, perhaps with the output of U3D also displayed?

"...the traces on my protoboard were not in best shape..."
I once had a client mess with an elaborate protoboard circuit. He put grossly excessive current through one of the power distribution bus strips - right from one end to the other. It blew open the bus strip at every "gap" between each group of 5 socket points. Annoying, but quite an impressive accomplishment, nonetheless. He was the careful brother. The one with a whole bunch of degrees would have reduced my entire board to the molecules whence it came.

 

Just a thought, PSOC has gates and MSI components inside it that using
a GUI tool to wire up/route internally to pins. Basically drag and drop. Even
though this is wrapped around a processor and a lot of other stuff you do
not have to write code for doing the simple gate/counter stuff. Even using the
more complex components, like PWM, timer, many only need a one line start
instruction (in case you are not a programmer).

The tool is free http://www.cypress.com/products/psoc-creator-integrated-design-environment-ide

Low cost boards -

http://www.cypress.com/documentatio...oc-5lp-prototyping-kit-onboard-programmer-and $10 hi end
http://www.cypress.com/documentation/development-kitsboards/psoc-4-cy8ckit-049-4xxx-prototyping-kits $4 low end
http://www.cypress.com/documentation/development-kitsboards/cy8ckit-042-psoc-4-pioneer-kit $30 low end arduino footprint

Getting started -

Google "psoc 101 videos", lessons 1 - 16 (you only have to watch first 3 or 4 to get an idea).Tool even has a state machine wizard
where you can create state machines that run in its HW w/o code (or with). Example video on making traffic light solution.




Regards, Dana.