CD4020 and gates problem

Discussion in 'Digital Circuit Design' started by bushrat, Mar 11, 2018.

  1. bushrat

    Thread Starter Member

    Nov 29, 2014
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    Hello all,
    Knowing myself, I'm probably missing something simple and stupid but cant see it.
    I'm trying to build a freq divider from 1 MHz to 25 Hz. Simulation works fine, everything is good to go.
    Trying it out on board is different story.
    upload_2018-3-11_17-48-1.png
    Frequency going in is fine, CD4020 works fine. problem now is with gates.
    From the simulation, once gate D is active (high output), it should reset the counter, but it does not.
    All it does is pull down the signal to 0V and keeps on counting. On o-scope output of D gate is always flat. I know the signal would be instant and very short, but I'm not seeing anything...
     
  2. MrChips

    Moderator

    Oct 2, 2009
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    Are you using TTL versions of 7474 and 7408?
    That is a no-no. You should not mix logic families.
    Switch to CMOS versions such as 74HC74 and 74HC08.
     
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  3. bushrat

    Thread Starter Member

    Nov 29, 2014
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    MH7474
    MC74HC4020N
    DM74LS08N
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    In addition to mixing logic devices from different families, which is asking for trouble unless you very carefully make sure that you are using them in a way that is compatible, you are also playing in the world of asynchronous logic. As soon as one of the internal FF that you are monitoring resets, your reset signal goes away even if the others haven't. Asynchronous logic design is not for the feint of heart; YOU become responsible for ensuring that you have no critical races or the possibility of glitches any where in your design that might affect it's behavior. You have the potential for both.
     
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  5. bushrat

    Thread Starter Member

    Nov 29, 2014
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    Its been a while since I build anything like this. It's also been a while since I was in school for electronics. I know I'm doing something wrong.
    I'm just doing electronics as hobby, not for work... if anything gets damaged (components), it's on my budget..
     
  6. bushrat

    Thread Starter Member

    Nov 29, 2014
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    Since I do not have any CMOS 7408, any other way to make it work?
     
  7. MrChips

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    The first thing would be to put in an order for some 74HC74 and 74HC08 and any other 74HCxx logic gates that you might use in the future.

    As a simple test, remove the 7408 and feed back Q14 alone to the MR input. See if this works (but with a different divisor result). The reset signal is going to be sub-microseconds and hence you really have to set up your oscilloscope carefully if you want to see this. As an alternative, look at Q13 on the scope.
     
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  8. MrChips

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    Another thing I just thought of, do you have LEDs connected to the outputs of the CD4020 counter?
    If you do, that is another no-no, which I can explain later.
     
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  9. bushrat

    Thread Starter Member

    Nov 29, 2014
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    I have 74HC74, and it was not the problem, it worked fine, but replaced as instructed.

    I put Q14 to MR, and reset signal is narrow, 20 nS from rise to fall.
    Frequency on Q13 remained same (30.49 Hz)

    Edit: No LED's, simulation had probes for visual refrence only. My intention was to feed the signal from 7408 to CD4017.

    Edit 2: this was supposed to be final outcome:
    upload_2018-3-11_20-18-33.png
     
  10. sghioto

    Well-Known Member

    Dec 31, 2017
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    As long as the supply voltages are equal you can mix CMOS with TTL. In this case you have TTL driving CMOS so add a 4.7K pullup resistor on pins 10 and 11 on U2.
    SG
     
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  11. bushrat

    Thread Starter Member

    Nov 29, 2014
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    Circuit is being driven by common 5V (+/- 20 ma current draw). I tried adding 1k pull-up resistor to pin 11 on U2, but it had no effect, signal was being pulled to 0V, but if I disconnect the wire from MR on U2, I was getting a 4.4V signal on output of 7408 gate.
     
  12. AnalogKid

    AAC Fanatic!

    Aug 1, 2013
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    I don't see any problems with the logic mix you have. Standard TTL can drive CMOS above its transition level, and CMOS can drive LSTTL. To prevent unintentional metastable spikes from resetting the 4020 incorrectly, add a short R-C delay/lowpass filter between U3Dout and 4020 Reset. 25 Hz is 40 ms, so anything under 10 ms should be unnoticeable.

    U3D > 10K > 0.1 uF to GND > Reset

    ak
     
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  13. bushrat

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    Nov 29, 2014
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    AnalogKid. Will try it out when I get home today, Thanks.
     
  14. MrChips

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    I put your circuit on a breadboard and had no problems.
    Are you sure that your 7408 is wired correctly?
    What is the make and model of your oscilloscope?
    You should see a 400ns positive pulse going into MR.
     
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  15. bushrat

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    Nov 29, 2014
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    Tonight, i will post pics and readings of my circuit.
     
  16. ebp

    Well-Known Member

    Feb 8, 2018
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    "You should see a 400ns positive pulse going into MR."
    I would believe a tenth of that and it could be shorter. It is the sum of the propagation delay from MR of the counter to the Q14 counter output and from input to output of U3D (this particular path because there is only one gate delay whereas there are 3 delays for the others).

    If you use a simple RC you can make the output of U3D stay HIGH longer, but that is (almost) only because you are delaying the arrival of MR to the counter.
    When U3D goes high, the capacitor will begin to charge through the resistor. With standard CMOS, (i.e. not TTL-compatible input versions) as soon as the voltage on the cap reaches approximately Vdd/2 it will be interpreted, dubiously, as logic HIGH. The capacitor continues to charge slowly, keeping the MR input in what is normally an undefined voltage range. The amount of time it continues to charge is the MR-to-output propagation delay plus the delay through the gate. When the output of U3D has returned low, the cap begins to discharge, and in this case the discharge will be faster than the charge because of the asymmetric source-sink currents and voltages of LS. It is this discharge time alone that adds to the assertion time of MR. You'll see a longer pulse at the output of U3D but the assertion of MR at the counter input will still be very short - and unless the RC time constant is short it will never get to a clean logic 1 voltage level. The slow edge bad level isn't likely to be a problem in this case because the first thing MR sees internal to the counter IC is a buffer, and multiple 0-1-0-1 transitions, as might result from noise on the signal, aren't detrimental. If the signal were a clock, it could make a mess. Some improvement can be made to the pulse stretcher by putting a diode, cathode to cap, in parallel with the resistor, making the charge time shorter than the discharge. A schmitt trigger would both clean up edge speed and logic levels and help lengthen the pulse because of its hysteresis (e.g charge to 3 V for HIGH, must return to 1.5 V for LOW - not actual values; see e.g. 74HC14 or HC132 or HCT version data). With a schmitt trigger the diode could be eliminated.

    With the counter in question, if the delays and MR assertion time are looked at critically there is a good chance of generating a clean clear with just the gating. The typical MR assertion time required is only 6 ns, though the spec'd minimum is 16 ns at 4.5V & 25°C. The numbers necessary to be certain, minimum prop delay from MR to output and through the gate, are not spec'd.
     
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  17. MrChips

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    Typical propagation delay from Reset to Qn = 370ns @ Vdd = 5V.

    MC14020B Propagation Delay.jpg
     
  18. sghioto

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    Dec 31, 2017
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    From that description the MR input on U2 is shorted to ground.
    SG
     
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  19. AnalogKid

    AAC Fanatic!

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    Clock to Q1 is 260 ns and clock to Q14 is 1820 ns. This tells me that the "ripple" in this ripple counter is significant. The Reset pulse is initiated when Q5 goes high after the other four high order bits already are 1's, and terminated by Q14 when it goes low.

    ak
     
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  20. takao21203

    AAC Fanatic!

    Apr 28, 2012
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    Around the year 2000 I was pretty bored so I went to the universities libraries, decided to design a 40XX CMOS LCD clock only with logic gates.

    I didnt use LCD decoder or driver, but generated the waveforms required. Some 25 ICs or so, presetable counters. When powering up, a resetting and preloading sequence would execute.

    Why I mention it, ofcourse I had various ideas how to build the circuit, over the course of two weeks or three,

    A) the local electronics store didnt have certain ICs
    B) some ideas just didnt work properly in reality. For exactly these reasons, glitchy and improper signals.

    Then I came up with the idea to execute a sequence at powering up, by some very slow clocking. You could see the digits updating one after the other. It was a proper and satisfactional solution. For the sequence I think I used a shift register, when done it would inhibit itself, I cant remember exactly. But of course, various approaches for the fine details had to be tried.

    I did know you can have glitches and ultra short signals and toggling back and forth in the nanoseconds range, so if it didnt work, the approach had to be rearranged.

    An output feeding back to somewhere the output state is coming from, yes can give you glitches and oscillations, and you wonder why forever.

    Question here is if the register bits all reset at once or in some sequence or on a sliding scale. But Id rather say they do at once. There could be buffered and unbuffered variants.

    Usually in such a case, needed to "condition" the output before feeding back, means put through a monoflop,

    A) a delay is added
    B) the signal will persist for considerably longer time

    ( I think its a monoflop )
     
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