When specifying a mosfet driver bootstrap capacitor, do you go with the gate voltage or the source voltage? Can find many App notes on choosing a value for the cap but none mention the voltage to use. Unless I missed it in my reading. My gate voltage is 12V but my drain/source voltage will be ~100V.

 

When specifying a mosfet driver bootstrap capacitor, do you go with the gate voltage or the source voltage? Can find many App notes on choosing a value for the cap but none mention the voltage to use. Unless I missed it in my reading. My gate voltage is 12V but my drain/source voltage will be ~100V.

I was going to say the cap should never see the source-drain voltage and needs to be sized for only the voltage ∆V it actually sees. But without your actual schematic, I may be making an assumption about what the cap might see.

 

In any bootstrapped drivers I've ever used the bootstrap capacitor is charged from the low-side gate driver supply, so the cap needs to be rated for that voltage.

 

Discrete or inside a gate driver IC, it all depends on the circuit. The safe assumption is that the full Vds will appear across the cap. Multiply that by 2.

ak

 

Is your circuit in LTspice? Just check the voltage across the cap.

 

Pretty much all of the gate driver ICs work the same, the low side is used to ground the source to then charge the boot cap. One thing I did read is the boot cap is sometimes called a "floating" voltage source for the driver, to keep the gate voltage above the mosfets source voltage. Since the only ground referenced voltage would be my 12V, would using a 50V cap work? When the mosfet is conducting and the low side is off there would be no ground reference on the boot cap. I don't know how to use LTspice or would have done what Wayne suggested. The driver is the Fan7390 and is being used in the half bridge configuration.

 

When Q2 is ON Vs is pulled to about 0 V, so the voltage across Cboot will be 15 V minus (the drop across Rboot and Dboot). Rboot is just there to limit the peak current and usually small enough that the capacitor will charge fully in a single switching cycle, so you'll have about 14.3 V across Cboot. When Q2 turns off, the voltage at Vs, without additional info, is undefined. When Q1 turns on, it will go "Up to 600V". The voltage on Cboot doesn't change because Dboot is reverse biased. The charge on Cboot supplies the high side driver logic and the current to drive the gate of Q1.

A 50 volt capacitor is more than sufficient. In the old days, that was a common minimum voltage for leaded monolithic ceramic caps, but there are now SM types with lower ratings, so a 25 V part might be suitable. Beware of "high K" (high dielectric constant) ceramics. Some of them have horrendous voltage coefficient of capacitance and if you run them anywhere near rated voltage they can be 20% or even less of nominal capacitance. Generally the types with X in the first position of the temperature/tolerance characteristic (eg X7R, X5R, etc) are much better behaved than the Y or Z types.

 

The highest voltage across the capacitor will be when the transistor switches on, and the full load voltage is applied to the lower side of the capacitor.,and also to the diode above it, as a reverse bias. So the diode must be rated for more than the load supply voltage.

 

Maybe one of these application notes will help.

 

Maybe one of these application notes will help.

Thanks those are just a few of what I have read, but no real sense of boot cap voltage is given, they all tell how to calculate the value but not the voltage.

 

The highest voltage across the capacitor will be when the transistor switches on, and the full load voltage is applied to the lower side of the capacitor.,and also to the diode above it, as a reverse bias. So the diode must be rated for more than the load supply voltage.

That is just totally wrong. Since these are DC voltages, and a cap doesn't pass DC.

 

When Q2 is ON Vs is pulled to about 0 V, so the voltage across Cboot will be 15 V minus (the drop across Rboot and Dboot). Rboot is just there to limit the peak current and usually small enough that the capacitor will charge fully in a single switching cycle, so you'll have about 14.3 V across Cboot. When Q2 turns off, the voltage at Vs, without additional info, is undefined. When Q1 turns on, it will go "Up to 600V". The voltage on Cboot doesn't change because Dboot is reverse biased. The charge on Cboot supplies the high side driver logic and the current to drive the gate of Q1.

A 50 volt capacitor is more than sufficient. In the old days, that was a common minimum voltage for leaded monolithic ceramic caps, but there are now SM types with lower ratings, so a 25 V part might be suitable. Beware of "high K" (high dielectric constant) ceramics. Some of them have horrendous voltage coefficient of capacitance and if you run them anywhere near rated voltage they can be 20% or even less of nominal capacitance. Generally the types with X in the first position of the temperature/tolerance characteristic (eg X7R, X5R, etc) are much better behaved than the Y or Z types.

Thank you for that! I understood what is happening, but didn't know what cap voltage to use. I was assuming that 50V caps would work but then started doubting myself, after buying 50V caps. I don't know why this isn't shown any where, all they talk about is calculating the cap value to use. The caps I bought are the multi layer ceramics dipped with epoxy.

 

I hadn't seen one of ap notes Richard linked to previously. The part on coping with negative-going "undershoot" is very good.

The capacitor voltage I guess is one of those things that is supposed to be "obvious" - and it is, sort of, once you fully understand how the whole thing works. We aren't used to thinking of ICs where one part hangs out near ground and another whole section zings back and forth between groundish and something up to hundreds of volts. It really is quite an accomplishment to shift the control signal reliably.

Dipped multilayer cap can be all sorts of different dielectrics, so without more detail it is hard to say how well they will perform. With older one, even the high-K types, the voltage coefficient problem was generally less, for reasons I don't fully understand. Some of the newer leaded dipped types are actually SM caps with leads added. Anyway, with 50 V parts used at around 12 V, the reduction in capacitance shouldn't be too bad.

 

Dipped multilayer cap can be all sorts of different dielectrics, so without more detail it is hard to say how well they will perform. With older one, even the high-K types, the voltage coefficient problem was generally less, for reasons I don't fully understand. Some of the newer leaded dipped types are actually SM caps with leads added. Anyway, with 50 V parts used at around 12 V, the reduction in capacitance shouldn't be too bad.

Again thank you. I did some calculation on the value of my caps, and found my earlier caps aren't going to be large enough. The mosfets I'm driving are large SOT-227 type, with a Qg total of 560 nC. by the Silabs boot cap calculator that means I need around 1.8uF for the caps. Is it OK to use more than one cap in parallel to get the correct value?